[PATCH] memory: renesas-rpc-if: Fix IO state based on flash type

[Geert Uytterhoeven]

Hi Biju,

CC hyperbus, spi

On Wed, Aug 30, 2023 at 4:58 PM Biju Das <biju.das.jz at bp.renesas.com> wrote:
> Currently, RZ/G2L-alike SoCs use 2 different SPI serial flash memories
>  1) AT25QL128A  embedded in RZ/{G2UL,Five} SMARC EVKs
>  2) MT25QU512AB embedded in RZ/{G2L,G2LC,V2L} SMARC EVKs
>
> As per section 8.14 on the AT25QL128A hardware manual,
> IO1..IO3 must be set to Hi-Z state for this flash for fast read quad IO.
> Snippet from HW manual section 8.14:
> The upper nibble of the Mode(M7-4) controls the length of the next FAST
> Read Quad IO instruction through the inclusion or exclusion of the first
> byte instruction code. The lower nibble bits of the Mode(M3-0) are don't
> care. However, the IO pins must be high-impedance before the falling edge
> of the first data out clock.
>
> As per the Figure 20: QUAD INPUT/OUTPUT FAST READ on MT25QU512AB mentions
> IO1..IO2 to be in Hi-Z state and IO3 in '1' state
>
> Add a variable io3_fv to struct rpcif_priv and check the child
> node compatible value to detect micron flash and set IO1..IO3 states
> based on flash type.
>
> Signed-off-by: Biju Das <biju.das.jz at bp.renesas.com>

Thanks for your patch!

I guess this issue is not unique to Renesas platforms...

> --- a/drivers/memory/renesas-rpc-if.c
> +++ b/drivers/memory/renesas-rpc-if.c
> @@ -189,6 +189,7 @@ struct rpcif_priv {
>         u32 enable;             /* DRENR or SMENR */
>         u32 dummy;              /* DRDMCR or SMDMCR */
>         u32 ddr;                /* DRDRENR or SMDRENR */
> +       u32 io3_fv;
>  };
>
>  static const struct rpcif_info rpcif_info_r8a7796 = {
> @@ -367,7 +368,8 @@ int rpcif_hw_init(struct device *dev, bool hyperflash)
>                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
>                                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
>                                    RPCIF_CMNCR_BSZ(3),
> -                                  RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
> +                                  RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IO0FV(2) |
> +                                  RPCIF_CMNCR_IO2FV(3) | rpc->io3_fv |
>                                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
>         else
>                 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
> @@ -774,6 +776,12 @@ static int rpcif_probe(struct platform_device *pdev)
>                 return ret;
>         }
>
> +       if (rpc->info->type == RPCIF_RZ_G2L &&

Wouldn't this apply to non-RZ/G2L systems, too?

> +           of_device_is_compatible(flash, "micron,mt25qu512a"))
> +               rpc->io3_fv = RPCIF_CMNCR_IO3FV(1);
> +       else
> +               rpc->io3_fv = RPCIF_CMNCR_IO3FV(3);
> +
>         return 0;
>  }

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds