[PATCH 2/2] mtd: spi-nor: Disable the flash quad mode in spi_nor_restore()

[Tudor.Ambarus at microchip.com]

On 6/16/20 4:02 PM, Yicong Yang wrote:
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> If the flash's quad mode is enabled, it'll remain in the quad mode when
> it's removed. If we drive the flash next time in SPI/Dual mode, then
> problem occurs as the flash's quad enable bit is not cleared.

Please describe the problems that occur. When QE bit is one the flash
operates in Standard/Dual/Quad SPI modes. WP# and RESET#/HOLD# are
affected as they change their functionality to IO2 and IO3 when QE
is 1. Is there anything else?

While I find the intention good, there might be some problems here:
1/ w25q jvm variants come with QE "fixed" to 1. This probably means
that QE is not writable, and a writing of QE to zero will be ignored,
but we have to check.
2/S25FS128S: CR1NV[1] can set the default power-on state for the
CR1V[1] to 1, i.e. QE to be set to 1 at power-on by default. The
logic here complicates a bit, and maybe we'll have to amend the
patch.

> 
> Disable the quad mode in spi_nor_restore(), the flash will leave
> quad mode when remove. This will make sure the flash always enter the
> correct mode when loaded.
s/correct/ Standard/Dual SPI

Cheers,
ta