[PATCH v3] mtd: spi-nor: add support for GD25Q256

[Cyrille Pitchen]

Hi Andy,

Le 15/02/2017 à 11:15, Andy Yan a écrit :
> GD25Q256 is a 32MiB SPI Nor flash from Gigadevice.
> 
> Signed-off-by: Andy Yan <andy.yan at rock-chips.com>
> 
> ---
> 
> Changes in v3:
> - rebase on top of spi-nor tree
> - add SPI_NOR_4B_OPCODES flag
> 
> Changes in v2:
> - drop one line unnecessary modification
> 
>  drivers/mtd/spi-nor/spi-nor.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 70e52ff..34327ab 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -995,6 +995,11 @@ static const struct flash_info spi_nor_ids[] = {
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>  	},
> +	{
> +		"gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
> +			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> +			SPI_NOR_4B_OPCODES)
> +	},

I didn't check in the GD25Q256 datasheet to confirm but I guess we
should also add the SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB info->flags as
for all other GigaDevice SPI NOR memories. Could you please check this
point?

Otherwise, the patch looks good and almost ready to be merged :)

Best regards,

Cyrille

>  
>  	/* Intel/Numonyx -- xxxs33b */
>  	{ "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },
>