[PATCH v4] mtd: spi-nor: Add support for N25Q256A11

[Cyrille Pitchen]

Hi Nobuhiro,

Le 23/03/2017 à 00:04, Nobuhiro Iwamatsu a écrit :
> Add new Micron N25Q256A (N25Q256A11) 256Mbit NOR Flash in the list
> of supported devices. This chip has the same structure as the N25Q256A
> but ID and voltage (1V8) to use is different. Therefore, this adds
> N25Q256A11 as n25q256ax1.
> 
> In the future, for new Micron memories we could use the patterns
> "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
> 
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw at hitachi.com>

I've fixed your commit message then I've applied your patch to
github/spi-nor.

Indeed, the lines below must be placed after the "---" line otherwise
they would appear in the commit message.

> 
> v4: Update description and fix typo.
> v3: Use new name space.
>     n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
> v2: Set 0x20bb1b as n25q256a, and 0x20bb1b as n25q256.
> 
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 1ae872bfc3ba..2e02991d93aa 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1031,6 +1031,7 @@ static const struct flash_info spi_nor_ids[] = {
>  	{ "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
>  	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
>  	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
> +	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
>  	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>  	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>  	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> 

Best regards,

Cyrille