UBI on dual NAND chips

[Richard Weinberger]

Nathan,

On Thu, Sep 24, 2015 at 4:44 AM, Nathan Williams
<nathan.williams at flightdata.com.au> wrote:
> We are planning to use two 32GiB MLC NAND flash chips in a product using
> a SoC FPGA with two NAND interfaces. The motivation for wanting to use
> multiple NAND chips is to improve reliability, not capacity.

Using UBI on MLC is not supported yet.
IOW, you have been warned. ;-)

> From what I've read, it's possible to use UBI on a concatenated MTD.
> If I have two identical chips, will these be concatenated automatically?

You mean using the mtd_concat driver?

> Is creating a single UBI volume over the two NAND chips (and using UBIFS
> on it) the best way to make use of a redundant NAND chip? Would
> mirroring data on a second UBI volume offer additional improvements to
> data reliability?

Depends on how you define "data reliability".
You're looking for something like an MTD RAID1 to deal with a dead chip?

> Also, what's the current status of the "unstable bits issue"?

It is a known issue but nobody cared hard enough so far.
Mostly due to the fact that nobody actually can trigger it.

Can you trigger it? If so, I'd like to get access to that hardware
and have a look.

-- 
Thanks,
//richard