UBI/UBIFS: dealing with MLC's paired pages

[Karl Zhang 张双锣 (karlzhang)]

Hello

Actually, we are working on the paired pages problem too. We have on MLC 
chips and developed a hardware power control board to simulate the real power loss cycle.

We have many ideas to share with you.


1. emulating the paired-page case
	HW: Develop a power control daughter board to control the power supply to NAND, including voltage/ramp control.
	SW: Add a module in NAND controller, utilize power board to shut down NAND power when programming paired upper page.
		
 This is easy for us to reproduce paired-page case, in order to guarantee the power loss moment, we add use FPGA logic 
to control the power board and detect the status of NAND.


2. EC/VID header corruption
	As Boris's excellent summary mentioned, "duplicate the EC header in the VID header", I also believe this is a good 
	solution to protect EC, and we are doing this and testing on MLC.
	
	For VID header, I think skip pages will waste too many capacity, and SLC mode conjugation with GC will make PE cycling higher.

	We are developing another solution to store VID info into other page's OOB area in its own block, because UBI does not 
	use OOB and ECC code always not use all OOB area. 
	


We are still developing and testing these solutions to protect EC and VID on MLC.
		

All the above is my limited work on paired pages, and I am open to any new suggestions and cooperation.



-----Original Message-----
From: linux-mtd [mailto:linux-mtd-bounces at lists.infradead.org] On Behalf Of Andrea Scian
Sent: Friday, September 18, 2015 5:38 PM
To: dedekind1 at gmail.com; Richard Weinberger; Boris Brezillon
Cc: Iwo Mergler; Jeff Lauruhn (jlauruhn); Qi Wang 王起 "(qiwang)"; linux-mtd at lists.infradead.org; Brian Norris; David Woodhouse
Subject: Re: UBI/UBIFS: dealing with MLC's paired pages


Boris, Artem,

thanks to both of you for you detailed description.
I'll follow this development, for sure I'll learn a lot :-)

Kind Regards,

-- 

Andrea SCIAN

DAVE Embedded Systems

Il 18/09/2015 09:54, Artem Bityutskiy ha scritto:
> Hi Andrea,
>
> On Fri, 2015-09-18 at 09:17 +0200, Andrea Scian wrote:
>> I perfectly understand the reason why using nandsim (and powercut 
>> simulator in general) but, AFAIK, the powercut problem is hard to 
>> "simulate" because the main issue is when the device see a loss of 
>> power in the middle of an operation (page write or block erase)
>
> This is right, and no doubts real power cuts testing is the most 
> important thing.
>
> However, at the beginning, it is very hard to develop if you do not 
> have a quick way to verify your ideas. Simulation is exactly for this 
> - to make the first reliable draft. Once that work, you go to the 
> second stage - real HW testing.
>
> Real HW testing requires a real power cycle, no guarantees power cut 
> happens at the right moment, so you may spend hours emulating just one 
> paired-page case. Compare this to just running a script, and it 
> emulates you 100 paired-page cases during 10 minutes. And you can 
> emulate it easily at the interesting places, not just during the main 
> data writes.
>
> So, to recap, I suggest emulation to make the first draft, and then 
> start heavy real testing to shape the final solution.
>
> Artem.
>


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