UBIFS Corrupt during power failure

[Nicolas Pitre]

On Wed, 15 Apr 2009, Eric Holmberg wrote:
> From: Jamie Lokier [mailto:jamie at shareable.org] 
> > I don't remember if it was NOR, NAND or something else, but I remember
> > reading about some flash which supports 1 concurrent write and 1
> > erase, and thinking "oh that's clever, it means you can do streaming
> > writes or rapid fsync/database commits without long pauses 
> > for erasing".
> 
> The evolution seems to be:
>  1. Allow erase / program suspend to do a read from a different PEB (the
> chip I'm using supports this)
>  2. Allow simultaneous read while either erasing or programming a
> different PEB
>  3. Allow parallel operations on different flash banks
>  4. Combine NOR and NAND onto the same chip

Most NOR chips do allow for #1 and we support it.

Recent Intel NOR parts allow for #2 and we support it.

It is already possible to do #3, whether you have multiple 
identical chips mapped 
contigously mapped, or through the MTD concat layer.

I think #4 is rather odd and unprobable.

> My understanding is that the parallel operations are only valid on
> different flash banks, where a flash bank could be thought of
> conceptually as a separate flash chip.  I'm no flash memory expert by
> any means, so I'm sure there are some other systems out there.

A single bank made of several contigous chips (and not the parallel chip 
arrangement often used to have a larger bus) already offers parallel 
operation possibilities, as long as parallel accesses have a 
sufficiently large offset between them to target different chips.

> > Of course you can do that with two flash chips side by side :-)

Beware.  The "two flash chips side by side" often means your chips are 
put in parallel on the bus, having one chip providing the lowest 16 
data bits, and the other chip providing the upper 16 bits.  This allows 
for a 2x read throughput, however this means that the erase block size 
is also doubled, while erase latency remains the same.

> > Can MTD and/or UBI join two chips to look like a single partition in
> > that way and avoid pauses for erase by writing to the other part?
> 
> The CONFIG_MTD_CONCAT option will join multiple chips together into a
> single MTD device, but I haven't looked into the code to see if it
> allows simultaneous operations on the separate chips.

It does.

> Nothing like RAID0 on flash :)

Well, the concat layer does not offer any kind of stripe management. I 
think someone posted a set of patches a while ago to add such a 
capability though.


Nicolas