[PATCH] NAND hardware ECC controller on at91sam9263 / at91sam9260

[David Brownell]

On Wednesday 23 April 2008, Richard Genoud wrote:
> +static int at91_nand_calculate(struct mtd_info *mtd,
> +               const u_char *dat, unsigned char *ecc_code)
> +{
> +       struct nand_chip *nand_chip = mtd->priv;
> +       struct at91_nand_host *host = nand_chip->priv;
> +       uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
> +       unsigned int ecc_value;
> +
> +       /* get the first 2 ECC bytes */
> +       ecc_value = ecc_readl(host->ecc, PR) & AT91_ECC_PARITY;
> +
> +       ecc_code[eccpos[0]] = ecc_value & 0xFF;
> +       ecc_code[eccpos[1]] = (ecc_value >> 8) & 0xFF;

My copy of the sam9263 docs doesn't list an "ECC_PARITY" field
in the PR register ... just two masked fields, 0xfff0 and 0x000f
labeled WORDADDR and BITADDR respectively.  (Which evidently are
combined into a single opague 0xffff mask on block writes, and
are interpretable only on block reads.)

And the system header doesn't have an ECC_PARITY mask ... so I
get build errors with current GIT.


> +
> +       /* get the last 2 ECC bytes */
> +       ecc_value = ecc_readl(host->ecc, NPR) & AT91_ECC_NPARITY;
> +
> +       ecc_code[eccpos[2]] = ecc_value & 0xFF;
> +       ecc_code[eccpos[3]] = (ecc_value >> 8) & 0xFF;

That one builds OK.

I suggest you just remove the masks from the readl() lines.
They're not necessary.

- Dave


> +
> +       return 0;
> +}