Questions about NAND (double)bit errors

[Wolfgang Mües]

Hello,

I want to use JFFS2/MTD in an embedded Linux device with frequent
writes (worst case is 15 KBytes per 10 seconds, typical case is less than 10% 
of the worst case). The device will be a 512 MBit NAND SLC type from Hynix,
Samsung or STM. We have a working prototype, and we have read many NAND flash
papers available on the net, and the recent MTD mailing list archives.

Beside of wear leveling questions, there are program disturb errors 
(programming a page flips a bit in another page) and read disturb errors 
(reading a page flips a bit). Rates for these single-bit-errors are available
in publications from M-systems and Toshiba. 

But since single bit errors are easily corrected by ECC, I am more interested 
in errors where more than 1 bit is flipped in a 256 byte ECC area. We cannot 
calculate these error numbers from the single bit errors because we don't 
know if these errors are unrelated to each other. 

Is there any information available to estimate/calculate the remaining errors
after ECC correction? Or is there any information about first hand experience
of NAND stress tests or other real world experience?

Maybe the NAND project is terminated if I don't find anything about practical
reliability...

best regards
Wolfgang Muees
-- 
Wolfgang Muees                    Vor den Grashoefen 1
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