XIP & GCC optimization & halting

[Nicolas Pitre]

On Thu, 20 Oct 2005, Korolev, Alexey wrote:

> Nicolas,
> 
> Selecting of only one CFI buswidth and chip interleave helped for
> resolving this issue.
> cfi_cmdset001.o doesn't contain any reference to __udivsi3 __divsi3 and
> __ashrdi3 in data segment.
> 
> I made several tests no halts or kernel panics got appeared. 

Great!

> P/S 
> 1. I also tried to relocate some /arch/arm/lib code into RAM. It was
> very bad move because it caused kernel Data abort at the very beginning
> of kernel bootup process. Looks some code uses __divsi3 operations
> before memory got initialized.

Although I don't encourage it, that should have worked since enough of 
the kernel data should always be available even when memory is partially 
initialized.

> 2. I have a question about XIP and icache 
> 
> 	a. Execute kernel instructions from FLASH. Start filling of
>          icache pages by instructions from FLASH.
> 	b. Do_write_buffer call. Switching to READ_STATUS. 
> 	c. Finish filling of icache pages by instructions from FLASH.
>          (Part of icache is corrupted).

No, that can't happen since do_write_buffer() is marked __xipram and 
therefore lives in ram.  Also, the call to xip_enable() ensures that the 
instruction prefetch is recycled with xip_iprefetch() after the flash 
has been turned into data mode again.

> 	d. Return from Do_write_buffer 
> 	e. Execute instruction from FLASH which is presorted in icache.
> -> Data abort or kernel panic.

Should not happen (see above).


Nicolas