[Re: [RPX Classic/Lite and byte ordering]]

[Eric]

Tim,

Have you verified that a kernel compiled with this io.h
change still works properly on your system?  This sounds
shakey to me if your kernel was already working as a whole
without your changes.

I would think that using __raw_writeX and __raw_readX combined
with the appropriate endian setting in cfi_endian.h would have
the same effect without such a drastic change.  I am more concerned
about the statement that other folks with the same boardset do not
experience this problem-- likely, the correct fix is an endian-map
(similar in spirit to LART) in cfi_endian.h rather than io.h in such 
a case.  If you can find a mythical RPX system that does not have this
error, perhaps you can modify the driver to read/write/read/write some
location to determine if you have an 'affected' board or not.

E

Tim Bowman <tbowman at emware.com> wrote:

> Ta-Da.... I fixed the problem in include/asm-ppc/io.h:
> ...
> #define readb(addr) in_8((volatile u8 *)(addr))
> #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
> #if defined(CONFIG_APUS) || defined(RPXCLASSIC)
> #define readw(addr) (*(volatile u16 *) (addr))
> #define readl(addr) (*(volatile u32 *) (addr))
> #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
> #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
> #else

[ ... ]

> This solution doesn't explain why some of you haven't had this problem. 
> Maybe the flash really is wired up two different ways on RPX boards...



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