[PATCH v4 net-next 5/5] net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap"

[Vladimir Oltean]

Hi Frank,

On Tue, Mar 24, 2026 at 06:36:44AM +0000, Frank Wunderlich wrote:
> Hi,
> 
> looks like this patch breaks BPI-R3 serdes between mt7986 SoC and mt7531 switch in 7.0 (6.19 is ok).
> in ethtool i see only tx on mac but no rx. if i revert this patch i can ping through dsa-ports again.
> 
> i did not completely understanding the code with the default-pol as it is now splitted between rx and tx.
> 
> mt7986 and this board does not have mediatek,pnswap set, so the final  regmap_update_bits writes val=0,
> before there was only write to this register on invert mode...but i guess this should not break. Maybe some
> kind of timing issue between mac and switch?
> 
> maybe reverting this patch skips changes made here:
> bde1ae2d52ab 2026-01-19 net: pcs: pcs-mtk-lynxi: pass SGMIISYS OF node to PCS
> 
> I resend as last try was sending as html (option "always send as text" in webmailer seems to be ignored
> somehow, had to choose "unformatted" in this response too).
> 
> regards Frank

Sorry for the delay.

If writing val=0 breaks the link, I'm curious
(a) whether it still breaks if we don't write anything at all
(b) what was the register value originally

Could you please test the patch below and let me know what it prints,
and whether traffic passes with it applied?

-- >8 --
diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c
index c12f8087af9b..5c5f45b93b82 100644
--- a/drivers/net/pcs/pcs-mtk-lynxi.c
+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
@@ -126,7 +126,7 @@ static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs,
 {
 	struct fwnode_handle *fwnode = mpcs->fwnode, *pcs_fwnode;
 	unsigned int pol, default_pol = PHY_POL_NORMAL;
-	unsigned int val = 0;
+	unsigned int val = 0, tmp;
 	int ret;
 
 	if (fwnode_property_read_bool(fwnode, "mediatek,pnswap"))
@@ -153,8 +153,14 @@ static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs,
 	if (pol == PHY_POL_INVERT)
 		val |= SGMII_PN_SWAP_TX;
 
-	return regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
-				  SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX, val);
+	ret = regmap_read(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, &tmp);
+	if (ret)
+		return ret;
+
+	pr_err("SGMSYS_QPHY_WRAP_CTRL = 0x%x, intending to write 0x%lx\n",
+	       tmp, (tmp & ~(SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX)) | val);
+
+	return 0;
 }
 
 static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
-- >8 --