[PATCH 08/11] drm/mediatek: ovl: Implement support for Gamma

[Nícolas F. R. A. Prado]

On Tue, 2026-03-03 at 06:53 +0000, CK Hu (胡俊光) wrote:
> On Tue, 2025-12-23 at 16:44 -0300, Nícolas F. R. A. Prado wrote:
> > External email : Please do not click links or open attachments
> > until you have verified the sender or the content.
> > 
> > 
> > The OVL hardware allows selecting between different fixed transfer
> > functions for each layer through the Gamma setting. Available
> > functions are scRGB, BT.709, BT.2020 and HLG. Implement support for
> > it
> > and expose it as a colorop through the DRM plane color pipeline
> > uAPI.
> > 
> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 67
> > ++++++++++++++++++++++++++++++++-
> >  1 file changed, 65 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index 4eaa31541ccc..a70092c792a9 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -52,10 +52,16 @@
> >  #define OVL_CON_CLRFMT_10_BIT                          (1)
> >  #define DISP_REG_OVL_WCG_CFG1                  0x2d8
> >  #define IGAMMA_EN(layer)                               BIT(0 + 4 *
> > (layer))
> > +#define GAMMA_EN(layer)                                       
> > BIT(2 + 4 * (layer))
> >  #define DISP_REG_OVL_WCG_CFG2                  0x2dc
> >  #define IGAMMA_MASK(layer)                            
> > GENMASK((layer) * 4 + 1, (layer) * 4)
> >  #define IGAMMA_SCRGB                                   0
> >  #define IGAMMA_BT709                                   1
> > +#define GAMMA_MASK(layer)                             
> > GENMASK((layer) * 4 + 3, (layer) * 4 + 2)
> > +#define GAMMA_SCRGB                                    0
> > +#define GAMMA_BT709                                    1
> > +#define GAMMA_BT2020                                   2
> > +#define GAMMA_HLG                                      3
> >  #define DISP_REG_OVL_ADDR_MT8173               0x0f40
> >  #define DISP_REG_OVL_ADDR(ovl, n)              ((ovl)->data->addr
> > + 0x20 * (n))
> >  #define DISP_REG_OVL_HDR_ADDR(ovl, n)          ((ovl)->data->addr
> > + 0x20 * (n) + 0x04)
> > @@ -508,11 +514,41 @@ static int
> > mtk_ovl_colorop_curve_to_reg_val(enum drm_colorop_curve_1d_type
> > curve
> >                 return IGAMMA_SCRGB;
> >         case DRM_COLOROP_1D_CURVE_BT2020_OETF:
> >                 return IGAMMA_BT709;
> > +       case DRM_COLOROP_1D_CURVE_SRGB_EOTF:
> > +               return GAMMA_SCRGB;
> > +       case DRM_COLOROP_1D_CURVE_BT2020_INV_OETF:
> 
> Maybe DRM_COLOROP_1D_CURVE_BT2020_OETF?

That is the kind of thing that is just guessing unless we can verify
through writeback or through official documentation of the hardware.
Just because a block is called "Inverse Gamma" it doesn't guarantee
that all curves should have inverse in their names. Some specifications
define EOTF curves, others define OETF curves. The inverse curves are
the inverse functions of a given EOTF or OETF curve, which are often
mathematically derived and not explicitly mentioned in the specs.

As for the other comments I'll address them in a following version.

Thanks,
Nícolas
>