[PATCH 2/2] ufs: host: mediatek: Add VCC on delay for stability
ed.tsai at mediatek.com
ed.tsai at mediatek.com
Thu Mar 5 00:29:15 PST 2026
From: Ed Tsai <ed.tsai at mediatek.com>
Introduced a delay after enabling UFS5 VCC for MT6995 to ensure
voltage stability before refclk activation.
Signed-off-by: Ed Tsai <ed.tsai at mediatek.com>
---
drivers/ufs/host/ufs-mediatek.c | 11 +++++++++++
drivers/ufs/host/ufs-mediatek.h | 4 ++++
2 files changed, 15 insertions(+)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index b3daaa07e925..020302f8fbdf 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1960,6 +1960,8 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc) {
@@ -1971,6 +1973,15 @@ static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
hba->dev_quirks &= ~UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM;
}
+ /*
+ * Add a delay after enable UFS5 VCC to ensure the voltage is
+ * stable before the refclk enable.
+ */
+ if (hba->dev_info.wspecversion >= 0x0500 &&
+ (host->ip_ver == IP_VER_MT6995_A0 ||
+ host->ip_ver == IP_VER_MT6995_B0))
+ hba->quirks |= UFSHCD_QUIRK_VCC_ON_DELAY;
+
ufs_mtk_vreg_fix_vcc(hba);
ufs_mtk_vreg_fix_vccqx(hba);
ufs_mtk_fix_ahit(hba);
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 9747277f11e8..8547a6f04990 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -220,6 +220,10 @@ enum {
IP_VER_MT6991_B0 = 0x10470000,
IP_VER_MT6993 = 0x10480000,
+ /* UFSHCI 5.0 */
+ IP_VER_MT6995_A0 = 0x10490000,
+ IP_VER_MT6995_B0 = 0x10500000,
+
IP_VER_NONE = 0xFFFFFFFF
};
--
2.45.2
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