[PATCH v1 1/2] Documentation: dt: reset: add mediatek,syscon-reset binding

[peter.wang at mediatek.com]

From: Peter Wang <peter.wang at mediatek.com>

Add Device Tree binding documentation for the MediaTek SYSCON reset
controller (mediatek,syscon-reset). This binding describes a reset
controller that is part of a MediaTek SYSCON MFD block and manages
multiple reset lines within that block.

The reset lines are defined via the 'mediatek,reset-bits' property,
where each entry is a five-cell tuple specifying the register offsets
and bit positions for asserting and deasserting a reset line:

  <set_offset set_bit clear_offset clear_bit delay_us>

Consumers reference individual reset lines by index into this list
using the standard '#reset-cells = <1>' scheme.

An example is provided showing a UFS subsystem use case, where the
reset controller is instantiated as a child node of the UFS syscon
MFD node.

Signed-off-by: Peter Wang <peter.wang at mediatek.com>
---
 .../bindings/reset/mediatek,syscon-reset.yaml | 93 +++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/mediatek,syscon-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/mediatek,syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek,syscon-reset.yaml
new file mode 100644
index 000000000000..45520ae6f090
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,syscon-reset.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SYSCON Reset Controller
+
+maintainers:
+  - Peter Wang <peter.wang at mediatek.com>
+
+description: |
+  This describes a reset controller which is part of a MediaTek SYSCON block
+  and is designed to manage multiple reset lines within that block.
+
+  The node should be a child of a syscon MFD node; it uses the parent's
+  regmap and therefore does not require its own 'reg' property.
+
+  The reset specifier for consumers is an index into the 'mediatek,reset-bits'
+  list. For example, to reference the second reset line:
+
+    resets = <&ufs0cfgao_rst 1>;
+    reset-names = "hci_rst";
+
+properties:
+  compatible:
+    const: mediatek,syscon-reset
+
+  '#reset-cells':
+    const: 1
+    description:
+      The cell should contain the index into the 'mediatek,reset-bits'
+      property to select the specific reset line.
+
+  mediatek,reset-bits:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    minItems: 1
+    maxItems: 64
+    description: |
+      A list of reset bit definitions. Each reset line is defined by a
+      five-cell entry: <set_offset set_bit clear_offset clear_bit delay_us>.
+      The reset specifier in the consumer driver will be an index into
+      this list. Up to 64 reset lines are supported per controller instance.
+    items:
+      items:
+        - description: >
+            Register offset from the parent syscon base for asserting
+            the reset. Must be 4-byte aligned.
+          minimum: 0
+          multipleOf: 4
+        - description: >
+            Bit index (0-based) within the register for asserting reset.
+          minimum: 0
+          maximum: 31
+        - description: >
+            Register offset from the parent syscon base for deasserting
+            the reset. Must be 4-byte aligned.
+          minimum: 0
+          multipleOf: 4
+        - description: >
+            Bit index (0-based) within the register for deasserting reset.
+          minimum: 0
+          maximum: 31
+        - description: >
+            Minimum delay in microseconds between assertion and deassertion
+            during a full reset cycle. Use 0 if no delay is required.
+          minimum: 0
+          maximum: 1000000
+
+required:
+  - compatible
+  - '#reset-cells'
+  - mediatek,reset-bits
+
+additionalProperties: false
+
+examples:
+  - |
+    ufs0cfg_ao: syscon at 16840000 {
+        compatible = "mediatek,mt8183-ufs0cfg_ao", "syscon", "simple-mfd";
+        reg = <0x16840000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ufs0cfgao_rst: reset-controller {
+            compatible = "mediatek,syscon-reset";
+            #reset-cells = <1>;
+            mediatek,reset-bits =
+                <0x48  3  0x4c  3  100>,
+                <0x148 0  0x14c 0  100>,
+                <0x148 1  0x14c 1  100>,
+                <0x148 2  0x14c 2  0>;
+        };
+    };
-- 
2.45.2