[PATCH v5 16/16] pinctrl: airoha: add support of an7563 SoC
Mikhail Kshevetskiy
mikhail.kshevetskiy at iopsys.eu
Mon Jun 22 05:04:03 PDT 2026
it was moved from airoha-common.h starting from v2.
On 6/22/26 14:55, Matheus Sampaio Queiroga wrote:
> Em segunda-feira, 22 de junho de 2026, às 08:30:46 Horário Padrão de Brasília,
> Mikhail Kshevetskiy escreveu:
>> +/*
>> + * shared - named RG_SW_TOD_1PPS_MODE on AN7563. Only the LAN LED mode
>> + * bits and GSW_TOD_1PPS exist on AN7563 (no 2nd I2C, I2S or PON 1PPS).
>> + */
>> +#define REG_GPIO_2ND_I2C_MODE 0x0214
>> +#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
>> +#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
>> +#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
>> +#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
>> +#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
>> +#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
>> +#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
>> +#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
>> +#define GSW_TOD_1PPS_MODE_MASK BIT(1)
>> +
>> +/* shared */
>> +#define REG_GPIO_SPI_CS1_MODE 0x0218
>> +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
>> +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
>> +#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
>> +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
>> +#define GPIO_PCM_SPI_MODE_MASK BIT(16)
>> +#define GPIO_PCM2_MODE_MASK BIT(13)
>> +#define GPIO_PCM1_MODE_MASK BIT(12)
>> +#define GPIO_PCM_INT_MODE_MASK BIT(9)
>> +#define GPIO_PCM_RESET_MODE_MASK BIT(8)
>> +#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
>> +#define GPIO_SPI_CS4_MODE_MASK BIT(3)
>> +#define GPIO_SPI_CS3_MODE_MASK BIT(2)
>> +#define GPIO_SPI_CS2_MODE_MASK BIT(1)
>> +#define GPIO_SPI_CS1_MODE_MASK BIT(0)
>> +
>> +#define REG_GPIO_PON_MODE 0x021c
>> +/*
>> + * AN7563 specific: route the standalone pads to their GPIO function.
>> + * 0: pad keeps its base function, 1: pad is GPIO<n>.
>> + */
>> +#define UART_RXD_GPIO_MODE_MASK BIT(22) /* GPIO37 */
>> +#define UART_TXD_GPIO_MODE_MASK BIT(21) /* GPIO36
>> */ +#define SPI_MISO_GPIO_MODE_MASK BIT(20) /*
>> GPIO35 */ +#define SPI_MOSI_GPIO_MODE_MASK BIT(19)
>> /* GPIO34 */ +#define SPI_CS_GPIO_MODE_MASK BIT(18) /*
>> GPIO33 */ +#define SPI_CLK_GPIO_MODE_MASK BIT(17) /* GPIO32
>> */ +#define I2C_SDA_GPIO_MODE_MASK BIT(16) /* GPIO31 */
>> +#define I2C_SCL_GPIO_MODE_MASK BIT(15) /* GPIO30 */ +/*
>> shared */
>> +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
>> +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
>> +#define SIPO_RCLK_MODE_MASK BIT(11)
>> +/*
>> + * Note: on AN7563 GPIO_PCIE_RESET{0,1} select the GPIO function of the
>> + * PCIE_RESET pads (0: PCIe reset, 1: GPIO28/GPIO29).
>> + */
>> +#define GPIO_PCIE_RESET1_MASK BIT(10) /* GPIO29 */
>> +#define GPIO_PCIE_RESET0_MASK BIT(9) /* GPIO28 */
>> +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
>> +#define GPIO_HSUART_MODE_MASK BIT(5)
>> +#define GPIO_SIPO_MODE_MASK BIT(2)
>> +#define GPIO_PON_MODE_MASK BIT(0)
>> +
>> +/* shared */
>> +#define REG_NPU_UART_EN 0x0224
>> +#define JTAG_UDI_EN_MASK BIT(4)
>> +#define JTAG_DFD_EN_MASK BIT(3)
>> +
>> +/* LED MAP - shared */
>> +#define REG_LAN_LED0_MAPPING 0x027c
>> +#define REG_LAN_LED1_MAPPING 0x0280
>> +
>> +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
>> +#define LAN3_PHY_LED_MAP(_n)
>> FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) +
>> +#define LAN2_LED_MAPPING_MASK GENMASK(10, 😎
>> +#define LAN2_PHY_LED_MAP(_n)
>> FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) +
>> +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
>> +#define LAN1_PHY_LED_MAP(_n)
>> FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) +
>> +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
>> +#define LAN0_PHY_LED_MAP(_n)
>> FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) +
>> +/*
>> + * CONF - shared.
>> + * The AN7563 standalone IO conf registers use the same bit layout as
>> + * EN7581 (UART1_TXD/RXD are named UART_TXD/RXD on AN7563).
>> + */
>> +#define REG_I2C_SDA_E2 0x001c
>> +#define SPI_MISO_E2_MASK BIT(14)
>> +#define SPI_MOSI_E2_MASK BIT(13)
>> +#define SPI_CLK_E2_MASK BIT(12)
>> +#define SPI_CS0_E2_MASK BIT(11)
>> +#define PCIE1_RESET_E2_MASK BIT(9)
>> +#define PCIE0_RESET_E2_MASK BIT(8)
>> +#define UART1_RXD_E2_MASK BIT(3)
>> +#define UART1_TXD_E2_MASK BIT(2)
>> +#define I2C_SCL_E2_MASK BIT(1)
>> +#define I2C_SDA_E2_MASK BIT(0)
>> +
>> +#define REG_I2C_SDA_E4 0x0020
>> +#define SPI_MISO_E4_MASK BIT(14)
>> +#define SPI_MOSI_E4_MASK BIT(13)
>> +#define SPI_CLK_E4_MASK BIT(12)
>> +#define SPI_CS0_E4_MASK BIT(11)
>> +#define PCIE1_RESET_E4_MASK BIT(9)
>> +#define PCIE0_RESET_E4_MASK BIT(8)
>> +#define UART1_RXD_E4_MASK BIT(3)
>> +#define UART1_TXD_E4_MASK BIT(2)
>> +#define I2C_SCL_E4_MASK BIT(1)
>> +#define I2C_SDA_E4_MASK BIT(0)
>> +
>> +#define REG_GPIO_L_E2 0x0024
>> +#define REG_GPIO_L_E4 0x0028
>> +
>> +#define REG_I2C_SDA_PU 0x0044
>> +#define SPI_MISO_PU_MASK BIT(14)
>> +#define SPI_MOSI_PU_MASK BIT(13)
>> +#define SPI_CLK_PU_MASK BIT(12)
>> +#define SPI_CS0_PU_MASK BIT(11)
>> +#define PCIE1_RESET_PU_MASK BIT(9)
>> +#define PCIE0_RESET_PU_MASK BIT(8)
>> +#define UART1_RXD_PU_MASK BIT(3)
>> +#define UART1_TXD_PU_MASK BIT(2)
>> +#define I2C_SCL_PU_MASK BIT(1)
>> +#define I2C_SDA_PU_MASK BIT(0)
>> +
>> +#define REG_I2C_SDA_PD 0x0048
>> +#define SPI_MISO_PD_MASK BIT(14)
>> +#define SPI_MOSI_PD_MASK BIT(13)
>> +#define SPI_CLK_PD_MASK BIT(12)
>> +#define SPI_CS0_PD_MASK BIT(11)
>> +#define PCIE1_RESET_PD_MASK BIT(9)
>> +#define PCIE0_RESET_PD_MASK BIT(8)
>> +#define UART1_RXD_PD_MASK BIT(3)
>> +#define UART1_TXD_PD_MASK BIT(2)
>> +#define I2C_SCL_PD_MASK BIT(1)
>> +#define I2C_SDA_PD_MASK BIT(0)
>> +
>> +#define REG_GPIO_L_PU 0x004c
>> +#define REG_GPIO_L_PD 0x0050
>> +
>> +#define REG_PCIE_RESET_OD 0x018c
>> +#define PCIE1_RESET_OD_MASK BIT(1)
>> +#define PCIE0_RESET_OD_MASK BIT(0)
>> +
>> +/*
>> + * PWM MODE CONF - shared.
>> + * The AN7563 GPIO flash mode registers use the same layout as EN7581:
>> + * REG_GPIO_FLASH_MODE_CFG covers GPIO0-15, REG_GPIO_FLASH_MODE_CFG_EXT
>> + * covers GPIO16-31 (bits 0-15) and GPIO36+ (bits 16+). The SPI pads
>> + * (GPIO32-35) have no flash mode configuration bit.
>> + */
>> +#define REG_GPIO_FLASH_MODE_CFG 0x0034
>> +#define GPIO15_FLASH_MODE_CFG BIT(15)
>> +#define GPIO14_FLASH_MODE_CFG BIT(14)
>> +#define GPIO13_FLASH_MODE_CFG BIT(13)
>> +#define GPIO12_FLASH_MODE_CFG BIT(12)
>> +#define GPIO11_FLASH_MODE_CFG BIT(11)
>> +#define GPIO10_FLASH_MODE_CFG BIT(10)
>> +#define GPIO9_FLASH_MODE_CFG BIT(9)
>> +#define GPIO8_FLASH_MODE_CFG BIT(8)
>> +#define GPIO7_FLASH_MODE_CFG BIT(7)
>> +#define GPIO6_FLASH_MODE_CFG BIT(6)
>> +#define GPIO5_FLASH_MODE_CFG BIT(5)
>> +#define GPIO4_FLASH_MODE_CFG BIT(4)
>> +#define GPIO3_FLASH_MODE_CFG BIT(3)
>> +#define GPIO2_FLASH_MODE_CFG BIT(2)
>> +#define GPIO1_FLASH_MODE_CFG BIT(1)
>> +#define GPIO0_FLASH_MODE_CFG BIT(0)
>> +
>> +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
>> +#define GPIO37_FLASH_MODE_CFG BIT(17)
>> +#define GPIO36_FLASH_MODE_CFG BIT(16)
>> +#define GPIO31_FLASH_MODE_CFG BIT(15)
>> +#define GPIO30_FLASH_MODE_CFG BIT(14)
>> +#define GPIO29_FLASH_MODE_CFG BIT(13)
>> +#define GPIO28_FLASH_MODE_CFG BIT(12)
>> +#define GPIO27_FLASH_MODE_CFG BIT(11)
>> +#define GPIO26_FLASH_MODE_CFG BIT(10)
>> +#define GPIO25_FLASH_MODE_CFG BIT(9)
>> +#define GPIO24_FLASH_MODE_CFG BIT(8)
>> +#define GPIO23_FLASH_MODE_CFG BIT(7)
>> +#define GPIO22_FLASH_MODE_CFG BIT(6)
>> +#define GPIO21_FLASH_MODE_CFG BIT(5)
>> +#define GPIO20_FLASH_MODE_CFG BIT(4)
>> +#define GPIO19_FLASH_MODE_CFG BIT(3)
>> +#define GPIO18_FLASH_MODE_CFG BIT(2)
>> +#define GPIO17_FLASH_MODE_CFG BIT(1)
>> +#define GPIO16_FLASH_MODE_CFG BIT(0)
>> +
>> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
>> + { \
>> + .name = (gpio), \
>> + .regmap[0] = { \
>> + AIROHA_FUNC_MUX, \
>> + REG_GPIO_PON_MODE, \
>> + (mux_val), \
>> + (mux_val) \
>> + }, \
>> + .regmap_size = 1, \
>> + }
>> +
>> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
>> + { \
>> + .name = (gpio), \
>> + .regmap[0] = { \
>> + AIROHA_FUNC_PWM_EXT_MUX, \
>> + REG_GPIO_FLASH_MODE_CFG_EXT, \
>> + (mux_val), \
>> + 0 \
>> + }, \
>> + .regmap[1] = { \
>> + AIROHA_FUNC_MUX, \
>> + REG_GPIO_PON_MODE, \
>> + (smux_val), \
>> + (smux_val) \
>> + }, \
>> + .regmap_size = 2, \
>> + }
>> +
>> +/* PWM */
>> +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
>> + { \
>> + .name = (gpio), \
>> + .regmap[0] = { \
>> + AIROHA_FUNC_PWM_MUX, \
>> + REG_GPIO_FLASH_MODE_CFG, \
>> + (mux_val), \
>> + (mux_val) \
>> + }, \
>> + .regmap_size = 1, \
>> + }
>> +
>> +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
>> + { \
>> + .name = (gpio), \
>> + .regmap[0] = { \
>> + AIROHA_FUNC_PWM_EXT_MUX, \
>> + REG_GPIO_FLASH_MODE_CFG_EXT, \
>> + (mux_val), \
>> + (mux_val) \
>> + }, \
>> + .regmap_size = 1, \
>> + }
>> +
>> +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
>> + { \
>> + .name = (gpio), \
>> + .regmap[0] = { \
>> + AIROHA_FUNC_PWM_EXT_MUX, \
>> + REG_GPIO_FLASH_MODE_CFG_EXT, \
>> + (mux_val), \
>> + (mux_val) \
>> + }, \
>> + .regmap[1] = { \
>> + AIROHA_FUNC_MUX, \
>> + REG_GPIO_PON_MODE, \
>> + (smux_val), \
>> + (smux_val) \
>> + }, \
>> + .regmap_size = 2, \
>> + }
>> +
>> +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
>> + { \
>> + .name = (gpio), \
>> + .regmap[0] = { \
>> + AIROHA_FUNC_MUX, \
>> + REG_GPIO_2ND_I2C_MODE, \
>> + (mux_val), \
>> + (mux_val), \
>> + }, \
>> + .regmap[1] = { \
>> + AIROHA_FUNC_MUX, \
>> + REG_LAN_LED0_MAPPING, \
>> + (map_mask), \
>> + (map_val), \
>> + }, \
>> + .regmap_size = 2, \
>> + }
>> +
>> +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
>> + { \
>> + .name = (gpio), \
>> + .regmap[0] = { \
>> + AIROHA_FUNC_MUX, \
>> + REG_GPIO_2ND_I2C_MODE, \
>> + (mux_val), \
>> + (mux_val), \
>> + }, \
>> + .regmap[1] = { \
>> + AIROHA_FUNC_MUX, \
>> + REG_LAN_LED1_MAPPING, \
>> + (map_mask), \
>> + (map_val), \
>> + }, \
>> + .regmap_size = 2, \
>> + }
> These defines are similar to what we have in airoha-common.h, whatever is not
> the same add the define with the prefix and the defines that exist only have a
> different regmap, move to the add in the define parameter, do as was done in
> en7523
>
>
More information about the Linux-mediatek
mailing list