[PATCH v2] arm64: dts: mediatek: Add Mediatek mt8192 cpufreq device nodes

[AngeloGioacchino Del Regno]

Il 10/02/22 19:56, Nícolas F. R. A. Prado ha scritto:
> Hi again,
> please see my comment below.
> 
> On Thu, Feb 10, 2022 at 09:47:04AM -0500, Nícolas F. R. A. Prado wrote:
>> Hi Andrew,
>>
>> On Tue, Dec 29, 2020 at 02:31:11PM +0800, Andrew-sh.Cheng wrote:
>>> From: "Andrew-sh.Cheng" <andrew-sh.cheng at mediatek.com>
>>>
>>> Correct dts node name in patch v1: performance-domain
>>> This patch depends on [1] and [2].
>>>
>>> [1]http://lists.infradead.org/pipermail/linux-mediatek/2020-November/019378.html
>>> [2]https://patchwork.kernel.org/project/linux-mediatek/patch/1607586516-6547-3-git-send-email-hector.yuan@mediatek.com/
>>
>> Those two series are now merged, so no dependencies missing for this patch any
>> longer.
>>
>> Please rebase this patch, as there are some conflicts. I've already verified it,
>> and after you rebase I can send a reviewed-by.
>>
>> Thanks,
>> Nícolas
>>
>>>
>>> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng at mediatek.com>
>>> ---
>>>   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
>>>   1 file changed, 14 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 69d45c7b31f1..a907ee7e650a 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -39,6 +39,7 @@
>>>   			compatible = "arm,cortex-a55";
>>>   			reg = <0x000>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 0>;
>>>   			clock-frequency = <1701000000>;
>>>   			next-level-cache = <&l2_0>;
>>>   			capacity-dmips-mhz = <530>;
>>> @@ -49,6 +50,7 @@
>>>   			compatible = "arm,cortex-a55";
>>>   			reg = <0x100>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 0>;
>>>   			clock-frequency = <1701000000>;
>>>   			next-level-cache = <&l2_0>;
>>>   			capacity-dmips-mhz = <530>;
>>> @@ -59,6 +61,7 @@
>>>   			compatible = "arm,cortex-a55";
>>>   			reg = <0x200>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 0>;
>>>   			clock-frequency = <1701000000>;
>>>   			next-level-cache = <&l2_0>;
>>>   			capacity-dmips-mhz = <530>;
>>> @@ -69,6 +72,7 @@
>>>   			compatible = "arm,cortex-a55";
>>>   			reg = <0x300>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 0>;
>>>   			clock-frequency = <1701000000>;
>>>   			next-level-cache = <&l2_0>;
>>>   			capacity-dmips-mhz = <530>;
>>> @@ -79,6 +83,7 @@
>>>   			compatible = "arm,cortex-a76";
>>>   			reg = <0x400>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 1>;
>>>   			clock-frequency = <2171000000>;
>>>   			next-level-cache = <&l2_1>;
>>>   			capacity-dmips-mhz = <1024>;
>>> @@ -89,6 +94,7 @@
>>>   			compatible = "arm,cortex-a76";
>>>   			reg = <0x500>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 1>;
>>>   			clock-frequency = <2171000000>;
>>>   			next-level-cache = <&l2_1>;
>>>   			capacity-dmips-mhz = <1024>;
>>> @@ -99,6 +105,7 @@
>>>   			compatible = "arm,cortex-a76";
>>>   			reg = <0x600>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 1>;
>>>   			clock-frequency = <2171000000>;
>>>   			next-level-cache = <&l2_1>;
>>>   			capacity-dmips-mhz = <1024>;
>>> @@ -109,6 +116,7 @@
>>>   			compatible = "arm,cortex-a76";
>>>   			reg = <0x700>;
>>>   			enable-method = "psci";
>>> +			performance-domains = <&performance 1>;
>>>   			clock-frequency = <2171000000>;
>>>   			next-level-cache = <&l2_1>;
>>>   			capacity-dmips-mhz = <1024>;
>>> @@ -194,6 +202,12 @@
>>>   		compatible = "simple-bus";
>>>   		ranges;
>>>   
>>> +		performance: performance-controller at 0011bc00 {
> 
> Actually there is a warning being introduced here on dtbs_check:
> 
> 	soc: 'performance-controller at 0011bc00' does not match any of the regexes: '@(0|[1-9a-f][0-9a-f]*)$', '^[^@]+$', 'pinctrl-[0-9]+'
> 		From schema: [...]/dtschema/schemas/simple-bus.yaml
> 
> So you should also change the address to not start with zeros: 11bc00
> 
> Thanks,
> Nícolas
> 
>>> +			compatible = "mediatek,cpufreq-hw";
>>> +			reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
>>> +			#performance-domain-cells = <1>;
>>> +		};
>>> +
>>>   		gic: interrupt-controller at c000000 {
>>>   			compatible = "arm,gic-v3";
>>>   			#interrupt-cells = <4>;
>>> -- 
>>> 2.12.5

Hello Andrew,

are you still interested in upstreaming this patch?
If you are, please update it with the suggested changes.

Thank you,
Angelo