[PATCH] irqchip/gic-v3: Ensure change to DS is visible

[Marc Zyngier]

On Wed, 30 Sep 2026 17:11:23 +0100,
Vladimir Murzin <vladimir.murzin at arm.com> wrote:
> 
> Sashiko reported missing GIC synchronization when the
> FLAGS_WORKAROUND_INSECURE path modifies DS. Specifically, an immediate
> read of the DS state after the write might not observe the effect of
> that write, which can lead to misreporting the DS state.
> 
> Updates to the DS bit are tracked by RWP, so poll it after the write
> before proceeding to read back the DS state.
> 
> Signed-off-by: Vladimir Murzin <vladimir.murzin at arm.com>
> ---
>  drivers/irqchip/irq-gic-v3.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index 6e1fa5b247fc..181f6eb11732 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -164,6 +164,7 @@ static inline bool gic_dist_security_disabled(void)
>  
>  static bool cpus_have_security_disabled __ro_after_init;
>  static bool cpus_have_group0 __ro_after_init;
> +static void gic_dist_wait_for_rwp(void);
>  
>  static void __init gic_prio_init(void)
>  {
> @@ -179,6 +180,7 @@ static void __init gic_prio_init(void)
>  			val = readl_relaxed(gic_data.dist_base + GICD_CTLR);
>  			val |= GICD_CTLR_DS;
>  			writel_relaxed(val, gic_data.dist_base + GICD_CTLR);
> +			gic_dist_wait_for_rwp();
>  
>  			ds = gic_dist_security_disabled();
>  			if (ds)

Ah, well spotted. FWIW:

Reviewed-by: Marc Zyngier <maz at kernel.org>

	M.

-- 
Jazz isn't dead. It just smells funny.