[PATCH v2 3/3] arm64: dts: imx95: convert eDMA to per-channel child nodes
Peng Fan (OSS)
peng.fan at oss.nxp.com
Tue Sep 29 23:26:11 PDT 2026
From: Peng Fan <peng.fan at nxp.com>
Convert edma2 and edma3 from flat interrupt arrays at the parent node
to per-channel child nodes (dma-channel@<addr>). Each child carries
its own reg (real per-channel MMIO region) and interrupts property.
edma2 (64 channels at 0x42000000):
- Channel N at 0x42010000 + N * 0x8000 (size 0x8000)
- Paired interrupts: SPI 128-159, two channels per SPI
edma3 (64 channels at 0x42210000):
- Channel N at 0x42220000 + N * 0x8000 (size 0x8000)
- Paired interrupts: SPI 256-287, two channels per SPI
edma1 (imx93-edma3, 31 channels with 1:1 non-paired interrupts) is
left unchanged as it uses a different interrupt scheme.
Assisted-by: LLM
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
arch/arm64/boot/dts/freescale/imx95.dtsi | 774 ++++++++++++++++++++++++++-----
1 file changed, 646 insertions(+), 128 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index d20c2498b9aa..64570703ce6c 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -635,148 +635,666 @@ edma2: dma-controller at 42000000 {
compatible = "fsl,imx95-edma5";
reg = <0x42000000 0x210000>;
#dma-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
dma-channels = <64>;
/* channels 0 and 1 reserved for V2X fast hash */
dma-channel-mask = <0x3>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
clock-names = "dma";
+
+ dma-channel at 42010000 {
+ reg = <0x42010000 0x8000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42018000 {
+ reg = <0x42018000 0x8000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42020000 {
+ reg = <0x42020000 0x8000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42028000 {
+ reg = <0x42028000 0x8000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42030000 {
+ reg = <0x42030000 0x8000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42038000 {
+ reg = <0x42038000 0x8000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42040000 {
+ reg = <0x42040000 0x8000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42048000 {
+ reg = <0x42048000 0x8000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42050000 {
+ reg = <0x42050000 0x8000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42058000 {
+ reg = <0x42058000 0x8000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42060000 {
+ reg = <0x42060000 0x8000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42068000 {
+ reg = <0x42068000 0x8000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42070000 {
+ reg = <0x42070000 0x8000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42078000 {
+ reg = <0x42078000 0x8000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42080000 {
+ reg = <0x42080000 0x8000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42088000 {
+ reg = <0x42088000 0x8000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42090000 {
+ reg = <0x42090000 0x8000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42098000 {
+ reg = <0x42098000 0x8000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420a0000 {
+ reg = <0x420a0000 0x8000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420a8000 {
+ reg = <0x420a8000 0x8000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420b0000 {
+ reg = <0x420b0000 0x8000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420b8000 {
+ reg = <0x420b8000 0x8000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420c0000 {
+ reg = <0x420c0000 0x8000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420c8000 {
+ reg = <0x420c8000 0x8000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420d0000 {
+ reg = <0x420d0000 0x8000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420d8000 {
+ reg = <0x420d8000 0x8000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420e0000 {
+ reg = <0x420e0000 0x8000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420e8000 {
+ reg = <0x420e8000 0x8000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420f0000 {
+ reg = <0x420f0000 0x8000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 420f8000 {
+ reg = <0x420f8000 0x8000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42100000 {
+ reg = <0x42100000 0x8000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42108000 {
+ reg = <0x42108000 0x8000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42110000 {
+ reg = <0x42110000 0x8000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42118000 {
+ reg = <0x42118000 0x8000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42120000 {
+ reg = <0x42120000 0x8000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42128000 {
+ reg = <0x42128000 0x8000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42130000 {
+ reg = <0x42130000 0x8000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42138000 {
+ reg = <0x42138000 0x8000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42140000 {
+ reg = <0x42140000 0x8000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42148000 {
+ reg = <0x42148000 0x8000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42150000 {
+ reg = <0x42150000 0x8000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42158000 {
+ reg = <0x42158000 0x8000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42160000 {
+ reg = <0x42160000 0x8000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42168000 {
+ reg = <0x42168000 0x8000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42170000 {
+ reg = <0x42170000 0x8000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42178000 {
+ reg = <0x42178000 0x8000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42180000 {
+ reg = <0x42180000 0x8000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42188000 {
+ reg = <0x42188000 0x8000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42190000 {
+ reg = <0x42190000 0x8000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42198000 {
+ reg = <0x42198000 0x8000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421a0000 {
+ reg = <0x421a0000 0x8000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421a8000 {
+ reg = <0x421a8000 0x8000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421b0000 {
+ reg = <0x421b0000 0x8000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421b8000 {
+ reg = <0x421b8000 0x8000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421c0000 {
+ reg = <0x421c0000 0x8000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421c8000 {
+ reg = <0x421c8000 0x8000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421d0000 {
+ reg = <0x421d0000 0x8000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421d8000 {
+ reg = <0x421d8000 0x8000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421e0000 {
+ reg = <0x421e0000 0x8000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421e8000 {
+ reg = <0x421e8000 0x8000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421f0000 {
+ reg = <0x421f0000 0x8000>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 421f8000 {
+ reg = <0x421f8000 0x8000>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42200000 {
+ reg = <0x42200000 0x8000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42208000 {
+ reg = <0x42208000 0x8000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
edma3: dma-controller at 42210000 {
compatible = "fsl,imx95-edma5";
reg = <0x42210000 0x210000>;
#dma-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
dma-channels = <64>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
clock-names = "dma";
+
+ dma-channel at 42220000 {
+ reg = <0x42220000 0x8000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42228000 {
+ reg = <0x42228000 0x8000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42230000 {
+ reg = <0x42230000 0x8000>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42238000 {
+ reg = <0x42238000 0x8000>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42240000 {
+ reg = <0x42240000 0x8000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42248000 {
+ reg = <0x42248000 0x8000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42250000 {
+ reg = <0x42250000 0x8000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42258000 {
+ reg = <0x42258000 0x8000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42260000 {
+ reg = <0x42260000 0x8000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42268000 {
+ reg = <0x42268000 0x8000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42270000 {
+ reg = <0x42270000 0x8000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42278000 {
+ reg = <0x42278000 0x8000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42280000 {
+ reg = <0x42280000 0x8000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42288000 {
+ reg = <0x42288000 0x8000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42290000 {
+ reg = <0x42290000 0x8000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42298000 {
+ reg = <0x42298000 0x8000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422a0000 {
+ reg = <0x422a0000 0x8000>;
+ interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422a8000 {
+ reg = <0x422a8000 0x8000>;
+ interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422b0000 {
+ reg = <0x422b0000 0x8000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422b8000 {
+ reg = <0x422b8000 0x8000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422c0000 {
+ reg = <0x422c0000 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422c8000 {
+ reg = <0x422c8000 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422d0000 {
+ reg = <0x422d0000 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422d8000 {
+ reg = <0x422d8000 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422e0000 {
+ reg = <0x422e0000 0x8000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422e8000 {
+ reg = <0x422e8000 0x8000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422f0000 {
+ reg = <0x422f0000 0x8000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 422f8000 {
+ reg = <0x422f8000 0x8000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42300000 {
+ reg = <0x42300000 0x8000>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42308000 {
+ reg = <0x42308000 0x8000>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42310000 {
+ reg = <0x42310000 0x8000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42318000 {
+ reg = <0x42318000 0x8000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42320000 {
+ reg = <0x42320000 0x8000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42328000 {
+ reg = <0x42328000 0x8000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42330000 {
+ reg = <0x42330000 0x8000>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42338000 {
+ reg = <0x42338000 0x8000>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42340000 {
+ reg = <0x42340000 0x8000>;
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42348000 {
+ reg = <0x42348000 0x8000>;
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42350000 {
+ reg = <0x42350000 0x8000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42358000 {
+ reg = <0x42358000 0x8000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42360000 {
+ reg = <0x42360000 0x8000>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42368000 {
+ reg = <0x42368000 0x8000>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42370000 {
+ reg = <0x42370000 0x8000>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42378000 {
+ reg = <0x42378000 0x8000>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42380000 {
+ reg = <0x42380000 0x8000>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42388000 {
+ reg = <0x42388000 0x8000>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42390000 {
+ reg = <0x42390000 0x8000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42398000 {
+ reg = <0x42398000 0x8000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423a0000 {
+ reg = <0x423a0000 0x8000>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423a8000 {
+ reg = <0x423a8000 0x8000>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423b0000 {
+ reg = <0x423b0000 0x8000>;
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423b8000 {
+ reg = <0x423b8000 0x8000>;
+ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423c0000 {
+ reg = <0x423c0000 0x8000>;
+ interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423c8000 {
+ reg = <0x423c8000 0x8000>;
+ interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423d0000 {
+ reg = <0x423d0000 0x8000>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423d8000 {
+ reg = <0x423d8000 0x8000>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423e0000 {
+ reg = <0x423e0000 0x8000>;
+ interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423e8000 {
+ reg = <0x423e8000 0x8000>;
+ interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423f0000 {
+ reg = <0x423f0000 0x8000>;
+ interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 423f8000 {
+ reg = <0x423f8000 0x8000>;
+ interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42400000 {
+ reg = <0x42400000 0x8000>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42408000 {
+ reg = <0x42408000 0x8000>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42410000 {
+ reg = <0x42410000 0x8000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma-channel at 42418000 {
+ reg = <0x42418000 0x8000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
mu7: mailbox at 42430000 {
--
2.51.0
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