[PATCH 5/6] arm64: insn: operate on MSR/MRS sysreg field via defines

[Ada Couprie Diaz]

Replace the few instances of hard-coded system register offset and masks
used to operate on MSR/MRS instructions with defines.
This will allow re-use in future commits while making the connection
between those values more explicit.

While we are here, mark `aarch64_insn_extract_system_reg()` `noinstr`
so it can be safe to use in alternative pacthing callbacks.

Changing the mask used in `aarch64_insn_gen_mrs()` to exclude
the lower bits does not change behaviour,
as `aarch64_insn_encode_register()` already clears the bits
used to encode the target register.

Signed-off-by: Ada Couprie Diaz <ada.coupriediaz at arm.com>
---
 arch/arm64/include/asm/insn.h | 3 +++
 arch/arm64/lib/insn.c         | 8 ++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 40f13d28a5fd7..03620f67a3e47 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -753,6 +753,9 @@ static __always_inline u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type)
 	return insn;
 }
 
+#define AARCH64_INSN_SYSREG_OFFSET	5
+#define AARCH64_INSN_SYSREG_MASK	GENMASK(19, 5)
+
 u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
 			 enum aarch64_insn_system_register sysreg);
 
diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index 5c37f3a4c402b..2edc5a9c0a9c8 100644
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -1362,9 +1362,9 @@ u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
 /*
  * Extract the Op/CR data from a msr/mrs instruction.
  */
-u32 aarch64_insn_extract_system_reg(u32 insn)
+noinstr u32 aarch64_insn_extract_system_reg(u32 insn)
 {
-	return (insn & 0x1FFFE0) >> 5;
+	return (insn & AARCH64_INSN_SYSREG_MASK) >> AARCH64_INSN_SYSREG_OFFSET;
 }
 
 bool aarch32_insn_is_wide(u32 insn)
@@ -1566,8 +1566,8 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
 {
 	u32 insn = aarch64_insn_get_mrs_value();
 
-	insn &= ~GENMASK(19, 0);
-	insn |= sysreg << 5;
+	insn &= ~AARCH64_INSN_SYSREG_MASK;
+	insn |= sysreg << AARCH64_INSN_SYSREG_OFFSET;
 	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
 					    insn, result);
 }
-- 
2.43.0