[PATCH 06/10] arm64: dts: st: Add SDMMC2 and SDMMC3 nodes on stm32mp251

[Alexandre TORGUE]

Hi Marek

On 7/11/26 22:59, Marek Vasut wrote:
> Add DT nodes for the remaining SDMMC controllers 2 and 3.
> 
> Signed-off-by: Marek Vasut <marex at nabladev.com>
> ---
> Cc: Alexandre Torgue <alexandre.torgue at foss.st.com>
> Cc: Bartosz Golaszewski <brgl at kernel.org>
> Cc: Conor Dooley <conor+dt at kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
> Cc: Linus Walleij <linusw at kernel.org>
> Cc: Rob Herring <robh at kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: kernel at dh-electronics.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-gpio at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org
> Cc: linux-stm32 at st-md-mailman.stormreply.com
> ---
>   arch/arm64/boot/dts/st/stm32mp251.dtsi | 30 ++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
> index 66f3f83b8731f..6e985f115b195 100644
> --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
> @@ -1667,6 +1667,36 @@ sdmmc1: mmc at 48220000 {
>   				status = "disabled";
>   			};
>   
> +			sdmmc2: mmc at 48230000 {
> +				compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x00353180>;
> +				reg = <0x48230000 0x400>, <0x44230800 0x8>;
> +				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc CK_KER_SDMMC2>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC2_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <166000000>;

I merged some weeks ago a patch introducing SDMCC2. max-freq is 120000000. I'll keep this patch adding SDMMC3, and increasing SDMMC2 max freq.

> +				access-controllers = <&rifsc 77>;
> +				status = "disabled";
> +			};
> +
> +			sdmmc3: mmc at 48240000 {
> +				compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x00353180>;
> +				reg = <0x48240000 0x400>, <0x44230c00 0x8>;
> +				interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc CK_KER_SDMMC3>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC3_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <166000000>;
> +				access-controllers = <&rifsc 78>;
> +				status = "disabled";
> +			};
> +
>   			ethernet1: ethernet at 482c0000 {
>   				compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
>   				reg = <0x482c0000 0x4000>;