[PATCH v3 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR

[Tushar Nimkar]

Hi Conor,

Thanks for review.

On 9/23/2026 10:11 PM, Conor Dooley wrote:
> On Wed, Sep 23, 2026 at 12:46:31PM +0530, Tushar Nimkar wrote:
>> From: Anirudha Sarangi <anirudha.sarangi at amd.com>
>>
>> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
>> (Control and Status Register) interrupt controller.
> This sounds like a very odd name for an interrupt controller.
> What else does this block do?
>
> You've actually got a 0x1000 carve out in the example, starting at a
> round number, so I suspect this is "fine" and if there's other features
> required later you've not painted yourself into a corner by defining a
> device for one register. The driver having a starting offset of 0x24 is
> another point in your favour.

The SMMU_CSR is a Xilinx-specific integration block for the ARM SMMUv3. 
It provides interrupt enable, status, and clear registers for SMMU 
interrupt sources before forwarding them to the parent GIC. The binding 
models the CSR block as a whole, allowing future integration-specific 
functionality to be added if needed.

>
> I'm inclined to ack this, I just want to see an answer first.

thanks  a much !!

-Tushar

>
> Cheers,
> Conor.
>> The SMMU CSR block acts as a vendor-specific interrupt controller
>> in front of the ARM SMMUv3, providing registers to enable and clear
>> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
>> Interrupts must be acknowledged in this block before being forwarded
>> to the parent interrupt controller (e.g. GIC).
>>
>> Signed-off-by: Anirudha Sarangi <anirudha.sarangi at amd.com>
>> Co-developed-by: Tushar Nimkar <tushar.nimkar at amd.com>
>> Signed-off-by: Tushar Nimkar <tushar.nimkar at amd.com>
>> ---
>>   .../xlnx,versal-net-smmu-csr.yaml                  | 75 ++++++++++++++++++++++
>>   1 file changed, 75 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml b/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml
>> new file mode 100644
>> index 000000000000..38b63e51b732
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml
>> @@ -0,0 +1,75 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/interrupt-controller/xlnx,versal-net-smmu-csr.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Xilinx Versal NET SMMU CSR Interrupt Controller
>> +
>> +maintainers:
>> +  - Anirudha Sarangi <anirudha.sarangi at amd.com>
>> +  - Tushar Nimkar <tushar.nimkar at amd.com>
>> +
>> +description: |
>> +  The Versal NET platform includes a Xilinx-specific SMMU CSR (Control and
>> +  Status Register) block that acts as an intermediate interrupt controller
>> +  for ARM SMMUv3.
>> +
>> +  The block provides registers to enable, disable and clear the
>> +  standard SMMUv3 interrupt sources (EVENTQ, CMDQ_SYNC, GERROR and PRIQ)
>> +  before forwarding them to the parent interrupt controller,
>> +  typically a GIC.
>> +
>> +  The controller receives one parent interrupt and demultiplexes CSR
>> +  status bits into the following child interrupt identifiers
>> +    0 - EVENTQ
>> +    1 - CMDQ_SYNC
>> +    2 - GERROR (GLOBAL)
>> +    3 - PRIQ
>> +
>> +allOf:
>> +  - $ref: /schemas/interrupt-controller.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: xlnx,versal-net-smmu-csr
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupt-controller: true
>> +
>> +  "#interrupt-cells":
>> +    const: 1
>> +    description: |
>> +     Single cell containing the child interrupt identifier
>> +      0 - EVENTQ
>> +      1 - CMDQ_SYNC
>> +      2 - GERROR (GLOBAL)
>> +      3 - PRIQ
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupt-controller
>> +  - "#interrupt-cells"
>> +  - interrupts
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    interrupt-controller at eca10000 {
>> +        compatible = "xlnx,versal-net-smmu-csr";
>> +        reg = <0xeca10000 0x1000>;
>> +        interrupt-controller;
>> +        #interrupt-cells = <1>;
>> +        interrupt-parent = <&gic>;
>> +        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
>> +    };
>>
>> -- 
>> 2.34.1
>>