[PATCH net-next 5/6] net: stmmac: mediatek: add support for TX deallocation adjustment feature

[Louis-Alexis Eyraud]

Hi Maxime,

On Wed, 2026-07-08 at 14:28 +0200, Louis-Alexis Eyraud wrote:
> Hi Maxime,
> 
> On Tue, 2026-07-07 at 11:11 +0200, Maxime Chevallier wrote:
> > Hi,
> > 
> > On 7/7/26 10:21, Louis-Alexis Eyraud wrote:
> > > The MT8189 SoC has in the Ethernet control 0 register from the
> > > peripheral configuration (pericfg) additional bits to adjust the
> > > TX
> > > deallocation.
> > > 
> > > In preparation of MT8189 SoC support, add its definition, use in
> > > the
> > > set_delay_v2 callback, and a support flag in the platform data.
> > 
> > Can you elaborate a bit on this ? I don't quite get what you mean
> > by
> > "tx deallocation", this seems to have to do with RGMII timings from
> > the register access pattern, but the local boolean flag for the
> > feature
> > is named "use_stage_fine", I'm failing to connect all the dots here
> > with the different terminology in use :(
> > 
> The data sheets I have, don't have info regarding this register, so
> I'll try to get more and improve commit and/or code description.
> 
> I'll also check if the register definition name is consistent
> (downstream driver and upstream u-boot use this stage fine term).
> use TXC phase shift control bit (bit 22, MT8195_RGMII_TXC_PHASE_CTRL)
> to insert the 2ns delay 
> The use_stage_fine feature flag could be renamed anyway to match what
> it does.
> 
Sorry for the delay on this topic. 
I did not get answers from Mediatek on this register until very
recently and as you have suspected, the description I got on these bits
the first time was incorrect and their usage was also incorrect.

These bits allow to insert a delay on TXC signal, to adjust the RGMII
timings. The bits 6 to 10 are used to value step (100ps per step) and
bit 11 to enable. So this patch inserts unconditionally this TX delay
with max value in MT8189 case and that is wrong.

There is an alternative way to insert this delay, as the MT8195 SoC
also provides a different set of bits (bits 0 to 5) which support is
already implemented in the driver (represented by
MT8195_DLY_GTXC_ENABLE and MT8195_DLY_GTXC_STAGES definitions). The
difference with the stage fine ones lies in the stage step value (280ps
per stage for MT8195), thus the fine term use for the new bits.
The MT8189 SoC also has these bits too but the stage step value is
different for this SoC (180ps per stage). The equivalent bits for
inserting a delay on RXC signal also have this same new stage
step value.

After discussing about these register bits use with a Mediatek
engineer, I was recommended not to use these new stage fine bits but
rather use the coarse ones (bit 0 to 5). I was also advised, that in
RGMII cases, when the link speed is 1Gbits, to prefer the use of TXC
phase shift control bit (bit 22, MT8195_RGMII_TXC_PHASE_CTRL) to insert
a fixed 2ns delay, and use the tx delay bits otherwise (for 10M/100M).
So, I'll drop this patch for v2.

Instead, I'll add new patches to rework the TX and RX delay handling,
to allow variants stage step values (the MT8195 stage step value use is
hardcoded in the MT8195 callbacks), and add the TXC phase shift control
use too.

Regards,
Louis-Alexis

> > > 
> > > Signed-off-by: Louis-Alexis Eyraud
> > > <louisalexis.eyraud at collabora.com>
> > > ---
> > >  .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c   | 25
> > > ++++++++++++++++------
> > >  1 file changed, 19 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> > > b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> > > index bcc0baef3f71..6b0a42b5839f 100644
> > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> > > @@ -37,7 +37,8 @@
> > >  #define ETH_FINE_DLY_RXC	BIT(0)
> > >  
> > >  /* Peri Configuration register for mt8189 */
> > > -#define MT8189_CTRL0_TXC_OUT_OP		BIT(20)
> > > +#define MT8189_CTRL0_TXC_OUT_OP			BIT(20)
> > 
> > Extra whitespace inserted here :)
> > 
> Oops, to be fixed in v2
> 
> Regards,
> Louis-Alexis
> 
> > Thanks,
> > 
> > Maxime