[PATCH 2/2] ARM: dts: imx6qdl: phycore-som: Add custom volt/freq table

[Primoz Fiser]

From: Yunus Bas <y.bas at phytec.de>

The PHYTEC phyCORE-i.MX6QDL SOM-modules are operating with a slightly
different voltage and frequency values in contrast to the generic
i.MX6Q/DL tables. The values have been adjusted to achieve the most
stable condition for the PHYTEC-modules. Introduce imx6q- and
imx6dl-phycore dtsi files with the modified power tables.

Signed-off-by: Yunus Bas <y.bas at phytec.de>
Signed-off-by: Primoz Fiser <primoz.fiser at norik.com>
---
 .../nxp/imx/imx6dl-phytec-mira-rdk-nand.dts   |  2 +-
 .../nxp/imx/imx6dl-phytec-phycore-som.dtsi    | 23 ++++++
 .../nxp/imx/imx6q-phytec-mira-rdk-emmc.dts    |  2 +-
 .../nxp/imx/imx6q-phytec-mira-rdk-nand.dts    |  2 +-
 .../dts/nxp/imx/imx6q-phytec-phycore-som.dtsi | 75 +++++++++++++++++++
 5 files changed, 101 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts
index d906a7f05aaa..8ec27080ca1e 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include "imx6dl.dtsi"
-#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6dl-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..de85c084ac8d
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-phytec-phycore-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <y.bas at phytec.de>
+ */
+
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+&cpu0 {
+	operating-points =
+		/* kHz    uV */
+		<996000 1275000>,
+		<792000 1175000>,
+		<396000 1150000>;
+};
+
+&cpu1 {
+	operating-points =
+		/* kHz    uV */
+		<996000 1275000>,
+		<792000 1175000>,
+		<396000 1150000>;
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts
index 322f071d972f..7d947762f3b9 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include "imx6q.dtsi"
-#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6q-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts
index 3f13726c8058..afbb6681a6b5 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 #include "imx6q.dtsi"
-#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6q-phytec-phycore-som.dtsi"
 #include "imx6qdl-phytec-mira.dtsi"
 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..ebe05d764357
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-phytec-phycore-som.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Yunus Bas <y.bas at phytec.de>
+ */
+
+#include "imx6qdl-phytec-phycore-som.dtsi"
+
+&cpu0 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
+
+&cpu1 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
+
+&cpu2 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
+
+&cpu3 {
+	operating-points =
+		/* kHz    uV */
+		<1200000 1300000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1175000>,
+		<396000  1075000>;
+	fsl,soc-operating-points =
+		/* ARM kHz  SOC-PU uV */
+		<1200000 1275000>,
+		<996000  1250000>,
+		<852000  1250000>,
+		<792000  1250000>,
+		<396000  1250000>;
+};
-- 
2.34.1