[PATCH v14 04/11] clk: realtek: Introduce common probe()

[Yu-Chun Lin [林祐君]]

Hi Jerome,

> > +++ b/drivers/clk/realtek/Kconfig
> > @@ -0,0 +1,30 @@
> > +# SPDX-License-Identifier: GPL-2.0-only config COMMON_CLK_REALTEK
> > +     tristate "Clock driver for Realtek SoCs"
> > +     depends on ARCH_REALTEK || COMPILE_TEST
> > +     default ARCH_REALTEK
> > +     help
> > +       Enable the common clock framework infrastructure for Realtek
> > +       system-on-chip platforms.
> > +
> > +       This provides the base support required by individual Realtek
> > +       clock controller drivers to expose clocks to peripheral devices.
> > +
> > +       If you have a Realtek-based platform, say Y.
> > +
> > +if COMMON_CLK_REALTEK
> > +
> > +config RTK_CLK_COMMON
> > +     tristate "Realtek Clock Common"
> > +     depends on RESET_CONTROLLER
> > +     select AUXILIARY_BUS
> > +     select REGMAP_MMIO
> > +     select RESET_RTK_COMMON
> 
> Is there compile time dependency with reset that I missed ?
> The point of the aux bus is to remove such dep
> 

Ack.

> > +     help
> > +       Common helper code shared by Realtek clock controller drivers.
> > +
> > +       This provides utility functions and data structures used by
> > +       multiple Realtek clock implementations, and include integration
> > +       with reset controllers where required.
> > +

[...]

> > +int rtk_clk_probe(struct platform_device *pdev, const struct
> > +rtk_clk_desc *desc) {
> > +     struct device *dev = &pdev->dev;
> > +     struct regmap *regmap;
> > +     void __iomem *base;
> > +     struct clk_hw *hw;
> > +     int i, ret;
> > +
> > +     base = devm_platform_ioremap_resource(pdev, 0);
> > +     if (IS_ERR(base))
> > +             return PTR_ERR(base);
> > +
> > +     regmap = devm_regmap_init_mmio(dev, base,
> &rtk_clk_regmap_config);
> > +     if (IS_ERR(regmap))
> > +             return PTR_ERR(regmap);
> > +
> > +     for (i = 0; i < desc->num_clks; i++)
> > +             desc->clks[i]->regmap = regmap;
> > +
> > +     for (i = 0; i < desc->clk_data->num; i++) {
> > +             hw = desc->clk_data->hws[i];
> > +             if (!hw)
> > +                     continue;
> > +
> > +             ret = devm_clk_hw_register(dev, hw);
> > +             if (ret)
> > +                     return dev_err_probe(dev, ret, "failed to register
> hw of clk%d\n", i);
> > +     }
> > +
> > +     ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> > +                                       desc->clk_data);
> > +     if (ret)
> > +             return dev_err_probe(dev, ret, "failed to add clock
> > + provider\n");
> > +
> > +     platform_set_drvdata(pdev, (void *)desc);
> > +
> > +     return rtk_reset_controller_register(dev, desc->aux_name,
> > + regmap);
> 
> sashiko report on Patch 10 is actually not a prexisting issue. it is here.
> Could you address it ?
> 

Will fix. I will swap the registration order of the reset controller and the
clock provider.

Best Regards,
Yu-Chun