[PATCH v1] arm64/boot: Disable trapping of PMZR_EL0 writes to EL2

[Oliver Upton]

On Tue, Sep 22, 2026 at 10:09:37PM +0100, Fuad Tabba wrote:
> Hi Oliver,
> 
> On Tue, 22 Sep 2026 20:47:58 +0100, Oliver Upton <oupton at kernel.org> wrote:
> [...]
> > We can trim 3 instructions from this by using the read-trap bits as the
> > starting point for the write-trap bits, like below. It also makes clear
> > the point that most of our trap bits are symmetrical for read and write.
> 
> I did consider that, and went the other way for two reasons.
> 
> The read side has three bits with no write-side counterpart
> (nPMSSDATA, nSPMDEVAFF_EL1, nSPMID), so copying x0 into x2 writes ones
> into three RES0 bits of HDFGWTR2_EL2. Harmless today, but it's this
> bug in reverse: the first revision that defines one of those positions
> in the write register turns the copy into a silent behaviour change.
> Building each mask from its own register's names can't do that.

My thinking was that we could have a third block, but...

> It also matches __init_el2_fgt, which already keeps x0 and x2 apart
> for HDFGRTR_EL2 and HDFGWTR_EL2. And even in that form the copy would
> have to sit just before the msr_s, after the SPE block, or
> nPMSDSFR_EL1 only lands in x0.

new feature-specific initialization blocks will make this an absolute
mess. So I agree, this is the right fix.

Reviewed-by: Oliver Upton <oupton at kernel.org>

Best,
Oliver