[PATCH v8 24/25] iommu/arm-smmu-v3-kvm: Enable nesting
Mostafa Saleh
smostafa at google.com
Tue Sep 22 06:12:57 PDT 2026
As now the hypervisor controls the command queue, stream table,
and shadows the stage-2 page table, we enable stage-2 translation
in case the host puts an STE in bypass or stage-1.
The hypervisor will control the S2 part of the STE and sanitize it.
Signed-off-by: Mostafa Saleh <smostafa at google.com>
---
.../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 109 +++++++++++++++++-
1 file changed, 103 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
index 5417a5c2bf58..39c97404e039 100644
--- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c
@@ -461,6 +461,57 @@ static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu)
return 0;
}
+static int smmu_attach_stage_2(struct arm_smmu_ste *ste)
+{
+ unsigned long vttbr, cfg;
+ unsigned long ts, sl, ic, oc, sh, tg, ps;
+ struct io_pgtable_cfg *pgt_cfg = &idmap_pgtable->cfg;
+
+ cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ste->data[0]));
+ if (!FIELD_GET(STRTAB_STE_0_V, le64_to_cpu(ste->data[0])) ||
+ (cfg == STRTAB_STE_0_CFG_ABORT)) {
+ return 0;
+ }
+ /* S2 is not advertised, that should never be attempted. */
+ if ((cfg == STRTAB_STE_0_CFG_S2_TRANS) ||
+ (cfg == STRTAB_STE_0_CFG_NESTED))
+ return -EINVAL;
+ vttbr = pgt_cfg->arm_lpae_s2_cfg.vttbr;
+ ps = pgt_cfg->arm_lpae_s2_cfg.vtcr.ps;
+ tg = pgt_cfg->arm_lpae_s2_cfg.vtcr.tg;
+ sh = pgt_cfg->arm_lpae_s2_cfg.vtcr.sh;
+ oc = pgt_cfg->arm_lpae_s2_cfg.vtcr.orgn;
+ ic = pgt_cfg->arm_lpae_s2_cfg.vtcr.irgn;
+ sl = pgt_cfg->arm_lpae_s2_cfg.vtcr.sl;
+ ts = pgt_cfg->arm_lpae_s2_cfg.vtcr.tsz;
+
+ ste->data[1] &= ~cpu_to_le64(STRTAB_STE_1_SHCFG);
+ ste->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING));
+
+ ste->data[1] &= ~cpu_to_le64(STRTAB_STE_1_EATS | STRTAB_STE_1_S2FWB | STRTAB_STE_1_STRW);
+
+ /* The host shouldn't write dwords 2 and 3, overwrite them. */
+ ste->data[2] = cpu_to_le64(FIELD_PREP(STRTAB_STE_2_VTCR,
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, ps) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, tg) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, sh) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, oc) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, ic) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, sl) |
+ FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, ts)) |
+ FIELD_PREP(STRTAB_STE_2_S2VMID, 0) |
+ STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2R |
+#ifdef __BIG_ENDIAN
+ STRTAB_STE_2_S2ENDI |
+#endif
+ STRTAB_STE_2_S2PTW);
+
+ ste->data[3] = cpu_to_le64(vttbr & STRTAB_STE_3_S2TTB_MASK);
+ /* Convert S1 => nested and bypass => S2 */
+ ste->data[0] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_0_CFG, cfg | BIT(1)));
+ return 0;
+}
+
static int smmu_get_host_l2_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid,
struct arm_smmu_ste *host_ste_out)
{
@@ -490,12 +541,40 @@ static int smmu_get_host_l2_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid,
return 0;
}
+struct smmu_ste_writer {
+ struct arm_smmu_entry_writer writer;
+ struct hyp_arm_smmu_v3_device *smmu;
+ u32 sid;
+};
+
+static void smmu_ste_writer_sync_entry(struct arm_smmu_entry_writer *writer)
+{
+ struct smmu_ste_writer *ste_writer =
+ container_of(writer, struct smmu_ste_writer, writer);
+ struct arm_smmu_cmd cfgi_cmd = arm_smmu_make_cmd_cfgi_ste(ste_writer->sid, true);
+
+ WARN_ON(smmu_send_cmd(ste_writer->smmu, &cfgi_cmd));
+}
+
+static const struct arm_smmu_entry_writer_ops smmu_ste_writer_ops = {
+ .get_used = arm_smmu_get_ste_used,
+ .get_update_safe = arm_smmu_get_ste_update_safe,
+ .sync = smmu_ste_writer_sync_entry,
+};
+
static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool leaf)
{
struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
- struct arm_smmu_ste *hyp_ste_ptr, *host_ste_ptr, host_ste_copy;
+ struct arm_smmu_ste *hyp_ste_ptr;
u64 *hyp_ste_base = strtab_hyp_base(smmu);
+ __le64 used[STRTAB_STE_DWORDS] = {};
+ struct arm_smmu_ste target = {};
int ret, i;
+ struct smmu_ste_writer ste_writer = {
+ .writer.ops = &smmu_ste_writer_ops,
+ .smmu = smmu,
+ .sid = sid,
+ };
/* Leaf = 0 is not supported, as the kernel driver. */
if (!leaf || !is_smmu_enabled(smmu) ||
@@ -511,7 +590,7 @@ static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool
return -E2BIG;
hyp_ste_ptr = &hyp_table[sid];
- host_ste_ptr = &host_table[sid];
+ memcpy(target.data, host_table[sid].data, STRTAB_STE_DWORDS << 3);
} else {
struct arm_smmu_strtab_l1 *l1tab = (struct arm_smmu_strtab_l1 *)hyp_ste_base;
u32 l1_idx = arm_smmu_strtab_l1_idx(sid);
@@ -520,8 +599,7 @@ static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool
if (l1_idx >= cfg->l2.num_l1_ents)
return -E2BIG;
- host_ste_ptr = &host_ste_copy;
- ret = smmu_get_host_l2_ste(smmu, sid, host_ste_ptr);
+ ret = smmu_get_host_l2_ste(smmu, sid, &target);
if (ret)
return ret;
@@ -541,8 +619,27 @@ static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool
hyp_ste_ptr = &l2ptr->stes[arm_smmu_strtab_l2_idx(sid)];
}
- for (i = 0; i < STRTAB_STE_DWORDS; ++i)
- WRITE_ONCE(hyp_ste_ptr->data[i], host_ste_ptr->data[i]);
+ /*
+ * Summary of each host emulated state vs real HW.
+ * | Host | HW |
+ * ==============================
+ * | V=0 | V=0 |
+ * | Abort | Abort |
+ * | Bypass | S2 |
+ * | S1 | S1+S2 |
+ */
+ ret = smmu_attach_stage_2(&target);
+ if (ret)
+ return ret;
+
+ /* The HW ignores unused fields, don't let the host set them. */
+ arm_smmu_get_ste_used(target.data, used);
+ for (i = 0; i < STRTAB_STE_DWORDS; i++)
+ target.data[i] &= used[i];
+
+ hyp_spin_lock(&smmu->hw_lock);
+ arm_smmu_write_entry(&ste_writer.writer, hyp_ste_ptr->data, target.data);
+ hyp_spin_unlock(&smmu->hw_lock);
return 0;
}
--
2.55.0.1082.g2b9226bbc0-goog
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