[PATCH v2] arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros

[Akashdeep Kaur]

Add virtual GPIO select mux macros for configuring the vgpio_sel
field in pad configuration registers. This field selects GPIO
controller routing. The meaning of each value is SoC-specific -
refer to the Technical Reference Manual for the specific SoC.

For example, on AM62L, values 0 and 1 select GPIO banks 0 and 2
respectively, while on J784S4, values 0-3 select different GPIO
controller pairs based on the pin. Pad configuration register
field details can be found in each SoC's Technical Reference
Manual (example: section 14.2.1.2.1 of [1]).

[1] AM62L TRM: https://www.ti.com/lit/ug/sprujb4a/sprujb4a.pdf

Signed-off-by: Akashdeep Kaur <a-kaur at ti.com>
---

Changes in v2:
  - Add all four PIN_VGPIO_SEL[0-3] macros instead of just two
  - Use generic value-based naming to support all K3 SoCs
  - Update commit message to clarify SoC-specific behavior
  - Link to v1: https://lore.kernel.org/all/20260917111539.3844577-1-a-kaur@ti.com/
  
---
 arch/arm64/boot/dts/ti/k3-pinctrl.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 4491898d8294..f6d262933fad 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -3,11 +3,12 @@
  * This header provides constants for pinctrl bindings for TI's K3 SoC
  * family.
  *
- * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/
  */
 #ifndef DTS_ARM64_TI_K3_PINCTRL_H
 #define DTS_ARM64_TI_K3_PINCTRL_H
 
+#define VGPIO_SEL_SHIFT         (4)
 #define WKUP_LVL_EN_SHIFT	(7)
 #define WKUP_LVL_POL_SHIFT	(8)
 #define DEBOUNCE_SHIFT		(11)
@@ -111,6 +112,11 @@
 #define PIN_WKUP_EN_LEVEL_HIGH		(WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
 #define PIN_WKUP_EN			(WKUP_ENABLE | WKUP_ON_EDGE)
 
+#define PIN_VGPIO_SEL0                  (0 << VGPIO_SEL_SHIFT)
+#define PIN_VGPIO_SEL1                  (1 << VGPIO_SEL_SHIFT)
+#define PIN_VGPIO_SEL2                  (2 << VGPIO_SEL_SHIFT)
+#define PIN_VGPIO_SEL3                  (3 << VGPIO_SEL_SHIFT)
+
 /* Default mux configuration for gpio-ranges to use with pinctrl */
 #define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
 
-- 
2.34.1