[PATCH v2 09/20] dt-bindings: arm: pmu: Allow power domains

[Rob Herring]

On Mon, Sep 14, 2026 at 01:54:37PM +0200, Linus Walleij wrote:
> Allow ARM PMU nodes to reference their power domain.
> 
> Signed-off-by: Linus Walleij <linusw at kernel.org>
> ---
>  Documentation/devicetree/bindings/arm/pmu.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
> index f47baaefcdac..305c1a9668f4 100644
> --- a/Documentation/devicetree/bindings/arm/pmu.yaml
> +++ b/Documentation/devicetree/bindings/arm/pmu.yaml
> @@ -88,6 +88,9 @@ properties:
>      # Don't know how many CPUs, so no constraints to specify
>      description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
>  
> +  power-domains:
> +    maxItems: 1

The PMUs are per core, so you really need to support more than 1. 
However, I think the PMUs would always be part of the core domain and 
the A9 docs[1] don't show any sort of PMU domain.

We already support power-domains in the CPU nodes, wouldn't that be more 
accurate?

Rob

[1] https://support.arm.com/documentation/ddi0407/b/clocking--resets--and-power-management/iem-support/cortex-a9-mpcore-power-domains