[PATCH 3/3] arm64: dts: rockchip: add vicap node to rk3576

[Michael Riesch]

Hi Amin,

Thanks for the patch, LGTM!

On 9/15/26 14:27, Amin Gattout wrote:
> Add the device tree node for the Video Capture (VICAP) unit of the
> RK3576 and its IOMMU, and connect the VICAP to the two MIPI CSI-2
> receivers that are usable with the MIPI D-PHYs in full mode.
> 
> Signed-off-by: Amin Gattout <amin.gattout at gmail.com>

Reviewed-by: Michael Riesch <michael.riesch at collabora.com>

Best regards,
Michael

> ---
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi | 83 ++++++++++++++++++++++++++++++++
>  1 file changed, 83 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index cbf8b70cc15a..0c46accf5657 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1323,6 +1323,81 @@ vdec_mmu: iommu at 27b00800 {
>  			rockchip,disable-mmu-reset;
>  			#iommu-cells = <0>;
>  		};
> +		vicap: video-capture at 27c10000 {
> +			compatible = "rockchip,rk3576-vicap";
> +			reg = <0x0 0x27c10000 0x0 0x800>;
> +			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
> +				 <&cru DCLK_VICAP>,
> +				 <&cru CLK_VICAP_I0CLK>, <&cru CLK_VICAP_I1CLK>,
> +				 <&cru CLK_VICAP_I2CLK>, <&cru CLK_VICAP_I3CLK>,
> +				 <&cru CLK_VICAP_I4CLK>;
> +			clock-names = "aclk", "hclk", "dclk",
> +				      "iclk", "iclk1", "iclk2", "iclk3", "iclk4";
> +			iommus = <&vicap_mmu>;
> +			power-domains = <&power RK3576_PD_VI>;
> +			resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
> +				 <&cru SRST_D_VICAP>,
> +				 <&cru SRST_VICAP_I0CLK>, <&cru SRST_VICAP_I1CLK>,
> +				 <&cru SRST_VICAP_I2CLK>, <&cru SRST_VICAP_I3CLK>,
> +				 <&cru SRST_VICAP_I4CLK>;
> +			reset-names = "arst", "hrst", "drst",
> +				      "irst0", "irst1", "irst2", "irst3", "irst4";
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				vicap_dvp: port at 0 {
> +					reg = <0x0>;
> +				};
> +
> +				vicap_mipi0: port at 1 {
> +					reg = <0x1>;
> +				};
> +
> +				vicap_mipi1: port at 2 {
> +					reg = <0x2>;
> +
> +					vicap_mipi1_input: endpoint {
> +						remote-endpoint = <&csi1_output>;
> +					};
> +				};
> +
> +				vicap_mipi2: port at 3 {
> +					reg = <0x3>;
> +				};
> +
> +				vicap_mipi3: port at 4 {
> +					reg = <0x4>;
> +
> +					vicap_mipi3_input: endpoint {
> +						remote-endpoint = <&csi3_output>;
> +					};
> +				};
> +
> +				vicap_mipi4: port at 5 {
> +					reg = <0x5>;
> +				};
> +
> +				vicap_toisp0: port at 10 {
> +					reg = <0x10>;
> +				};
> +			};
> +		};
> +
> +		vicap_mmu: iommu at 27c10800 {
> +			compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
> +			reg = <0x0 0x27c10800 0x0 0x100>;
> +			interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
> +			clock-names = "aclk", "iface";
> +			power-domains = <&power RK3576_PD_VI>;
> +			rockchip,disable-mmu-reset;
> +			#iommu-cells = <0>;
> +			status = "disabled";
> +		};
>  
>  		csi1: csi at 27c90000 {
>  			compatible = "rockchip,rk3576-mipi-csi2", "rockchip,rk3568-mipi-csi2";
> @@ -1346,6 +1421,10 @@ csi1_in: port at 0 {
>  
>  				csi1_out: port at 1 {
>  					reg = <1>;
> +
> +					csi1_output: endpoint {
> +						remote-endpoint = <&vicap_mipi1_input>;
> +					};
>  				};
>  			};
>  		};
> @@ -1372,6 +1451,10 @@ csi3_in: port at 0 {
>  
>  				csi3_out: port at 1 {
>  					reg = <1>;
> +
> +					csi3_output: endpoint {
> +						remote-endpoint = <&vicap_mipi3_input>;
> +					};
>  				};
>  			};
>  		};
>