[PATCH v4 3/4] arm64: dts: google: Add initial dts for frankel/blazer/mustang
Peter Griffin
peter.griffin at linaro.org
Fri Sep 18 12:05:04 PDT 2026
From: Douglas Anderson <dianders at chromium.org>
Add initial device trees for frankel (Pixel 10), blazer (Pixel 10
Pro) and mustang (Pixel 10 Pro XL). These device trees are enough to
boot to a serial prompt using an initramfs.
Currently only Laguna B0 silicon found in mass production phones is
officially supported. Further revisions such as A0 silicon and EVT
devices maybe added in the future if they are useful. As of today,
these device trees boot fine on EVT devices with A0 silicon.
A few things can be noted about these device trees:
1. They purposely choose to use the full 64-bit address and size cells
for the root node and the `soc at 0` node. Although I haven't tested
the need for this, I presume the arguments made in
commit bede7d2dc8f3 ("arm64: dts: qcom: sdm845: Increase address
and size cells for soc") would apply here.
2. Though it looks as if the UART is never enabled, the bootloader
knows to enable the UART when the console is turned on. Baud rate
is configurable in the bootloader so is never hardcoded in the
device tree.
Changes by Peter Griffin:
- Remove dtbo overlay approach and add individual board dts
- Update to lga-pixel-common naming like gs101-pixel-common
- Reorder nodes alpha-numerically by the node name
- Add ramoops reserved-memory (tested with console=pstore)
- Add reserved-memory for bootloader & gsa logs
- Add reserved-memory for Android BootLoader ABL (used on Watchdog
reset to extract boolotader logs / parse breadcrumbs / ramdump etc).
- Add osc 38.4Mhz fixed-clock
Signed-off-by: Douglas Anderson <dianders at chromium.org>
Co-developed-by: Peter Griffin <peter.griffin at linaro.org>
Signed-off-by: Peter Griffin <peter.griffin at linaro.org>
Tested-by: Brian Norris <briannorris at chromium.org>
Reviewed-by: Brian Norris <briannorris at chromium.org>
---
Changes in v3
* Use 0x0 instead of 0 consistently for new code (Krysztof)
* Remove 'ranges' from gic-v3 as no msi child node with unit address (Krysztof)
* Remove ufs0 alias and ufs placeholder node (Krysztof)
* Remove memory node from lga.dtsi (Krysztof)
It turns out bootloader adds the node anyway
* Use standard '/ {' not overlay style (Krysztof)
* Update alias to point at label (Brian)
* Drop GIC_CPU_MASK_SIMPLE for GICv3 interrupt controller (Shashiko)
* Fix dt-check-style --mode=strict warnings (Peter)
Changes in v2 (by Peter Griffin):
* Remove dtbo overlay approach and add individual board dts
* Update to lga-pixel-common naming like gs101-pixel-common
* Reorder nodes alpha-numerically by the node name
* Add ramoops reserved-memory (tested with console=pstore)
* Add reserved-memory for bootloader & gsa logs
* Add reserved-memory for Android BootLoader ABL (used on Watchdog
reset to extract boolotader logs / parse breadcrumbs / ramdump etc).
* Add osc 38.4Mhz fixed-clock
---
arch/arm64/boot/dts/google/Makefile | 5 +
arch/arm64/boot/dts/google/lga-blazer.dts | 15 +
arch/arm64/boot/dts/google/lga-frankel.dts | 15 +
arch/arm64/boot/dts/google/lga-mustang.dts | 15 +
arch/arm64/boot/dts/google/lga-pixel-common.dtsi | 22 ++
arch/arm64/boot/dts/google/lga.dtsi | 413 +++++++++++++++++++++++
6 files changed, 485 insertions(+)
diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile
index a6b187e2d6318..4e833b2561e08 100644
--- a/arch/arm64/boot/dts/google/Makefile
+++ b/arch/arm64/boot/dts/google/Makefile
@@ -1 +1,6 @@
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+
+dtb-$(CONFIG_ARCH_GOOGLE) += \
+ lga-blazer.dtb \
+ lga-frankel.dtb \
+ lga-mustang.dtb
diff --git a/arch/arm64/boot/dts/google/lga-blazer.dts b/arch/arm64/boot/dts/google/lga-blazer.dts
new file mode 100644
index 0000000000000..0894606624f8e
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-blazer.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Blazer Device Tree (Pixel 10 Pro)
+ *
+ * Copyright 2021-2023 Google LLC
+ */
+
+/dts-v1/;
+
+#include "lga-pixel-common.dtsi"
+
+/ {
+ model = "Blazer";
+ compatible = "google,lga-blazer", "google,lga";
+};
diff --git a/arch/arm64/boot/dts/google/lga-frankel.dts b/arch/arm64/boot/dts/google/lga-frankel.dts
new file mode 100644
index 0000000000000..7504222a728d4
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-frankel.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Frankel Device Tree (Pixel 10)
+ *
+ * Copyright 2021-2023 Google LLC
+ */
+
+/dts-v1/;
+
+#include "lga-pixel-common.dtsi"
+
+/ {
+ model = "Frankel";
+ compatible = "google,lga-frankel", "google,lga";
+};
diff --git a/arch/arm64/boot/dts/google/lga-mustang.dts b/arch/arm64/boot/dts/google/lga-mustang.dts
new file mode 100644
index 0000000000000..6ac0b5ef22ff2
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-mustang.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Mustang Device Tree (Pixel 10 Pro XL)
+ *
+ * Copyright 2021-2023 Google LLC
+ */
+
+/dts-v1/;
+
+#include "lga-pixel-common.dtsi"
+
+/ {
+ model = "Mustang";
+ compatible = "google,lga-mustang", "google,lga";
+};
diff --git a/arch/arm64/boot/dts/google/lga-pixel-common.dtsi b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi
new file mode 100644
index 0000000000000..5aaa2e5af8ec9
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Google Pixel 10 family common dtsi.
+ *
+ * Copyright 2024-2025 Google LLC.
+ */
+
+#include "lga.dtsi"
+
+/ {
+ aliases {
+ serial0 = &lsion_cli16_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+};
+
+&osc {
+ clock-frequency = <38400000>;
+};
diff --git a/arch/arm64/boot/dts/google/lga.dtsi b/arch/arm64/boot/dts/google/lga.dtsi
new file mode 100644
index 0000000000000..26a14b3a1b190
--- /dev/null
+++ b/arch/arm64/boot/dts/google/lga.dtsi
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Google Tensor G5 (laguna) SoC rev B0
+ *
+ * Copyright 2024-2025 Google LLC.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ osc: clock-38400000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hayes_0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x000>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <258>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd0>;
+ power-domain-names = "psci";
+ };
+
+ hayes_1: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x100>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <258>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd1>;
+ power-domain-names = "psci";
+ };
+
+ hunter_0: cpu at 200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a725";
+ reg = <0x200>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd2>;
+ power-domain-names = "psci";
+ };
+
+ hunter_1: cpu at 300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a725";
+ reg = <0x300>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd3>;
+ power-domain-names = "psci";
+ };
+
+ hunter_2: cpu at 400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a725";
+ reg = <0x400>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd4>;
+ power-domain-names = "psci";
+ };
+
+ hunter_3: cpu at 500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a725";
+ reg = <0x500>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd5>;
+ power-domain-names = "psci";
+ };
+
+ hunter_4: cpu at 600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a725";
+ reg = <0x600>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <891>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd6>;
+ power-domain-names = "psci";
+ };
+
+ hunterelp_0: cpu at 700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-x4";
+ reg = <0x700>;
+
+ #cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
+ enable-method = "psci";
+ power-domains = <&cpu_pd7>;
+ power-domain-names = "psci";
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&hayes_0>;
+ };
+
+ core1 {
+ cpu = <&hayes_1>;
+ };
+
+ core2 {
+ cpu = <&hunter_0>;
+ };
+
+ core3 {
+ cpu = <&hunter_1>;
+ };
+
+ core4 {
+ cpu = <&hunter_2>;
+ };
+
+ core5 {
+ cpu = <&hunter_3>;
+ };
+
+ core6 {
+ cpu = <&hunter_4>;
+ };
+
+ core7 {
+ cpu = <&hunterelp_0>;
+ };
+ };
+ };
+
+ domain-idle-states {
+ cluster_1_c3: cluster-1-c3 {
+ compatible = "domain-idle-state";
+
+ entry-latency-us = <325>;
+ exit-latency-us = <553>;
+ min-residency-us = <10000>;
+
+ idle-state-name = "cluster-1-c3";
+
+ arm,psci-suspend-param = <0x40010033>;
+ };
+
+ cluster_2_c3: cluster-2-c3 {
+ compatible = "domain-idle-state";
+
+ entry-latency-us = <345>;
+ exit-latency-us = <673>;
+ min-residency-us = <10000>;
+
+ idle-state-name = "cluster-2-c3";
+
+ arm,psci-suspend-param = <0x40010033>;
+ };
+
+ cluster_c4_deep: cluster-c4-deep {
+ compatible = "domain-idle-state";
+
+ entry-latency-us = <510>;
+ exit-latency-us = <1027>;
+ min-residency-us = <10000>;
+
+ idle-state-name = "cluster-c4-deep";
+
+ arm,psci-suspend-param = <0x40020333>;
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_big_c2: cpu-big-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <110>;
+ exit-latency-us = <413>;
+ min-residency-us = <3950>;
+
+ idle-state-name = "cpu-big-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+
+ cpu_lit_c2: cpu-lit-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <132>;
+ exit-latency-us = <296>;
+ min-residency-us = <3610>;
+
+ idle-state-name = "cpu-lit-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+
+ cpu_mid1_c2: cpu-mid1-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <130>;
+ exit-latency-us = <274>;
+ min-residency-us = <2720>;
+
+ idle-state-name = "cpu-mid1-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+
+ cpu_mid2_c2: cpu-mid2-c2 {
+ compatible = "arm,idle-state";
+
+ entry-latency-us = <130>;
+ exit-latency-us = <274>;
+ min-residency-us = <2720>;
+
+ idle-state-name = "cpu-mid2-c2";
+ local-timer-stop;
+
+ arm,psci-suspend-param = <0x40000003>;
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpucl1: power-domain-cluster-1 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_1_c3>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpucl2: power-domain-cluster-2 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_2_c3>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_lit_c2>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpu_pd1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_lit_c2>;
+ power-domains = <&cpu_top_cl>;
+ };
+
+ cpu_pd2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid1_c2>;
+ power-domains = <&cpucl1>;
+ };
+
+ cpu_pd3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid1_c2>;
+ power-domains = <&cpucl1>;
+ };
+
+ cpu_pd4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid1_c2>;
+ power-domains = <&cpucl1>;
+ };
+
+ cpu_pd5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid2_c2>;
+ power-domains = <&cpucl2>;
+ };
+
+ cpu_pd6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_mid2_c2>;
+ power-domains = <&cpucl2>;
+ };
+
+ cpu_pd7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_big_c2>;
+ power-domains = <&cpucl2>;
+ };
+
+ cpu_top_cl: power-domain-top-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_c4_deep>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+ * Store ramoops at a known location in DRAM, for access by the
+ * ABL following a crash-reset.
+ */
+ ramoops at 95200000 {
+ compatible = "ramoops";
+ reg = <0x0 0x95200000 0x0 0x400000>;
+ console-size = <0x200000>;
+ pmsg-size = <0x200000>;
+ };
+
+ /* bootloader logs */
+ bldr_log_reserved: bldr-log-reserved at 95600000 {
+ reg = <0x0 0x95600000 0x0 0x100000>;
+ no-map;
+ };
+
+ /* gsa logs */
+ gsa_reserved_log: gsa-reserved-log at a61b0000 {
+ reg = <0x0 0xa61b0000 0x0 0x00004000>;
+ no-map;
+ };
+
+ /* Android BootLoader (ABL) for ramdump/coredump processing */
+ abl at be000000 {
+ reg = <0x0 0xbe000000 0x0 0x1000000>;
+ no-map;
+ };
+ };
+
+ soc: soc at 0 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller at 5880000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x05880000 0x0 0x10000>,
+ <0x0 0x05900000 0x0 0x200000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&hayes_0 &hayes_1
+ &hunter_0 &hunter_1 &hunter_2
+ &hunter_3 &hunter_4>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&hunterelp_0>;
+ };
+ };
+ };
+
+ lsion_cli16_uart: serial at db62000 {
+ compatible = "google,lga-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x0db62000 0x0 0x100>;
+
+ clock-frequency = <200000000>;
+ interrupts = <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH 0>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
--
2.55.0.1082.g2b9226bbc0-goog
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