[PATCH v11 7/9] coresight: etm4x: exclude ss_status from drvdata->config
Yeoreum Yun
yeoreum.yun at arm.com
Fri Sep 18 10:13:37 PDT 2026
> Hi,
>
> Actually replied to v10 of this patch before I spotted v11. I'll repeat the
> comments here to keep them together.
Yeap. I confirmed but thanks again ;)
>
>
>
> On 9/15/26 12:34, Yeoreum Yun wrote:
> > The purpose of TRCSSCSRn register is to show status of
> > the corresponding Single-shot Comparator Control and input supports.
> > That means writable field's purpose for reset or restore from idle status
> > not for configuration.
> >
> > Therefore, exclude ss_status from drvdata->config and move it to drvdata.
> >
> > Before this patch, clearing the PENDING and STATUS bits when enabling
> > a perf session could trigger multiple single-shot events within
> > the same session. This issue will be addressed in a future patch;
>
> The hardware is designed to have multiple single shot events - the reset bit
> in TRCSSCCRn specifically programs this behaviour.
>
> But the basic point is correct there is no need to have the status register
> as part of the configurable set of registers.
Agree and Thanks for clarification!
>
>
>
> > this patch intentionally preserves the existing behavior.
> >
> > Reviewed-by: Leo Yan <leo.yan at arm.com>
> > Signed-off-by: Yeoreum Yun <yeoreum.yun at arm.com>
> > ---
> > drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 1 -
> > drivers/hwtracing/coresight/coresight-etm4x-core.c | 20 +++++++++-----------
> > drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++-----
> > drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++-
> > 4 files changed, 20 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > index d24f533c623d0..098aabd2b922c 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > off_mask = (offset & GENMASK(11, 5));
> > do {
> > CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
> > - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
> > CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
> > } while (0);
> > } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 70a5c0b4fad1c..9de0c268ff954 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
> > const struct etmv4_caps *caps = &drvdata->caps;
> > return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
> > - (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
> > + (drvdata->ss_status[n] & TRCSSCSRn_PC);
> > }
> > u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> > @@ -573,11 +573,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - /* always clear status bit on restart if using single-shot */
> > + /* always clear status and pending bits on restart if using single-shot */
> > if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> > - config->ss_status[i] &= ~TRCSSCSRn_STATUS;
> > + drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
> > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
> > + etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));
> > if (etm4x_sspcicrn_present(drvdata, i))
> > etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
> > }
> > @@ -1081,7 +1081,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
> > /* read the status of the single shot comparators */
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - config->ss_status[i] =
> > + drvdata->ss_status[i] =
> > etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > }
> > @@ -1162,12 +1162,9 @@ static void etm4_disable_sysfs(struct coresight_device *csdev)
> > drvdata, 1);
> > /*
> > - * Userspace may read ss_status and cntr_val through sysfs after
> > + * Userspace may read cntr_val through sysfs after
> > * the sysfs-session has been disabled.
> > */
> > - for (i = 0; i < caps->nr_ss_cmp; i++)
> > - config->ss_status[i] = active_config->ss_status[i];
> > -
> > for (i = 0; i < caps->nr_cntr; i++)
> > config->cntr_val[i] = active_config->cntr_val[i];
> > @@ -1525,8 +1522,9 @@ static void etm4_init_arch_data(void *info)
> > */
> > caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
> > for (i = 0; i < caps->nr_ss_cmp; i++) {
> > - drvdata->config.ss_status[i] =
> > - etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > + drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
> > + drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
> > + TRCSSCSRn_DA | TRCSSCSRn_INST);
>
> The unused bits in this register are RES0 - rendering this masking
> redundant.
There was some review for this whether RES0 versus clarifies the bit
we see. TBH, I tend to agree it's redundant. So I'll restore it.
Thanks!
>
> > }
> > /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> > caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index f6d053f73264c..50ef2e957300f 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -1833,8 +1833,8 @@ static ssize_t sshot_ctrl_store(struct device *dev,
> > raw_spin_lock(&drvdata->spinlock);
> > idx = config->ss_idx;
> > config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
> > - /* must clear bit 31 in related status register on programming */
> > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> > + /* must clear bit 31 and 30 in related status register on programming */
> > + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> > raw_spin_unlock(&drvdata->spinlock);
> > return size;
> > }
> > @@ -1848,7 +1848,7 @@ static ssize_t sshot_status_show(struct device *dev,
> > struct etmv4_config *config = &drvdata->config;
> > raw_spin_lock(&drvdata->spinlock);
> > - val = config->ss_status[config->ss_idx];
> > + val = drvdata->ss_status[config->ss_idx];
> > raw_spin_unlock(&drvdata->spinlock);
> > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > }
> > @@ -1885,8 +1885,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
> > raw_spin_lock(&drvdata->spinlock);
> > idx = config->ss_idx;
> > config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
> > - /* must clear bit 31 in related status register on programming */
> > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
> > + /* must clear bit 31 and 30 in related status register on programming */
> > + drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
> > raw_spin_unlock(&drvdata->spinlock);
> > return size;
> > }
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index ffde48b6b41b2..8c1c1364b1c44 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -213,6 +213,7 @@
> > #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
> > #define TRCSSCSRn_STATUS BIT(31)
> > +#define TRCSSCSRn_PENDING BIT(30)
>
> Minor nit - PENDING is ETE only - worth commenting in case a reader is
> looking at the ETMv4 spec.
Thanks. I'll add a little bit of comment!
>
> > #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
> > #define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
> > @@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
> > #define ETM_DEFAULT_ADDR_COMP 0
> > #define TRCSSCSRn_PC BIT(3)
> > +#define TRCSSCSRn_DV BIT(2)
> > +#define TRCSSCSRn_DA BIT(1)
> > +#define TRCSSCSRn_INST BIT(0)
>
> These new defs are redundant if the masking above is redundant
+1
Thanks!
[...]
--
Sincerely,
Yeoreum Yun
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