[PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang
Peter Griffin
peter.griffin at linaro.org
Fri Sep 18 10:01:14 PDT 2026
Hi Krzysztof,
Thank you for the time spent reviewing this and review feedback.
On Fri, 24 Jul 2026 at 07:59, Krzysztof Kozlowski <krzk at kernel.org> wrote:
>
> On Wed, Jul 22, 2026 at 10:55:55AM +0100, Peter Griffin wrote:
> > diff --git a/arch/arm64/boot/dts/google/lga-pixel-common.dtsi b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi
> > new file mode 100644
> > index 000000000000..57c318ab44c9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi
> > @@ -0,0 +1,23 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
> > +/*
> > + * Google Pixel 10 family common dtsi.
> > + *
> > + * Copyright 2024-2025 Google LLC.
> > + */
> > +
> > +#include "lga.dtsi"
> > +
> > +&{/} {
>
> This is overlay style, but the file is DTSI. Just use standard '/ {' -
> that's simple and obvious enough path.
I've fixed this and all the other review points made here in v3 (which
I will send out shortly). After seeing your recent DT cleanup patches
for Exynos/gs101 I've made it pass `dt-check-style --mode=strict ` as
well.
>
> > + chosen {
> > + stdout-path = "serial0";
> > + };
> > +
> > + aliases {
> > + serial0 = "/soc at 0/serial at db62000"; /* &lsion_cli16_uart */
> > + ufs0 = "/ufs-placeholder"; /* &ufs - TODO "/soc at 0/ufs at 3c400000" */
>
> UFS does not have aliases, please drop.
>
> > + };
> > +};
> > +
> > +&osc {
> > + clock-frequency = <38400000>;
> > +};
> > diff --git a/arch/arm64/boot/dts/google/lga.dtsi b/arch/arm64/boot/dts/google/lga.dtsi
> > new file mode 100644
> > index 000000000000..343156a8c039
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/google/lga.dtsi
> > @@ -0,0 +1,423 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
> > +/*
> > + * Google Tensor G5 (laguna) SoC rev B0
> > + *
> > + * Copyright 2024-2025 Google LLC.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + interrupt-parent = <&gic>;
> > +
> > + osc: clock-38400000 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + };
> > +
> > + cpus: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + hayes_0: cpu at 0 {
> > + compatible = "arm,cortex-a520";
> > + reg = <0x000>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <258>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd0>;
> > + };
> > +
> > + hayes_1: cpu at 100 {
> > + compatible = "arm,cortex-a520";
> > + reg = <0x100>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <258>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd1>;
> > + };
> > +
> > + hunter_0: cpu at 200 {
> > + compatible = "arm,cortex-a725";
> > + reg = <0x200>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <891>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd2>;
> > + };
> > +
> > + hunter_1: cpu at 300 {
> > + compatible = "arm,cortex-a725";
> > + reg = <0x300>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <891>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd3>;
> > + };
> > +
> > + hunter_2: cpu at 400 {
> > + compatible = "arm,cortex-a725";
> > + reg = <0x400>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <891>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd4>;
> > + };
> > +
> > + hunter_3: cpu at 500 {
> > + compatible = "arm,cortex-a725";
> > + reg = <0x500>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <891>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd5>;
> > + };
> > +
> > + hunter_4: cpu at 600 {
> > + compatible = "arm,cortex-a725";
> > + reg = <0x600>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <891>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd6>;
> > + };
> > +
> > + hunterelp_0: cpu at 700 {
> > + compatible = "arm,cortex-x4";
> > + reg = <0x700>;
> > +
> > + #cooling-cells = <2>;
> > + capacity-dmips-mhz = <1024>;
> > + device_type = "cpu";
> > + enable-method = "psci";
> > + power-domain-names = "psci";
> > + power-domains = <&cpu_pd7>;
> > + };
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&hayes_0>;
> > + };
> > + core1 {
> > + cpu = <&hayes_1>;
> > + };
> > + core2 {
> > + cpu = <&hunter_0>;
> > + };
> > + core3 {
> > + cpu = <&hunter_1>;
> > + };
> > + core4 {
> > + cpu = <&hunter_2>;
> > + };
> > + core5 {
> > + cpu = <&hunter_3>;
> > + };
> > + core6 {
> > + cpu = <&hunter_4>;
> > + };
> > + core7 {
> > + cpu = <&hunterelp_0>;
> > + };
> > + };
> > + };
> > +
> > + idle-states {
> > + entry-method = "psci";
> > +
> > + cpu_lit_c2: cpu-lit-c2 {
> > + compatible = "arm,idle-state";
> > +
> > + entry-latency-us = <132>;
> > + exit-latency-us = <296>;
> > + min-residency-us = <3610>;
> > +
> > + idle-state-name = "cpu-lit-c2";
> > + local-timer-stop;
> > +
> > + arm,psci-suspend-param = <0x40000003>;
> > + };
> > +
> > + cpu_mid1_c2: cpu-mid1-c2 {
> > + compatible = "arm,idle-state";
> > +
> > + entry-latency-us = <130>;
> > + exit-latency-us = <274>;
> > + min-residency-us = <2720>;
> > +
> > + idle-state-name = "cpu-mid1-c2";
> > + local-timer-stop;
> > +
> > + arm,psci-suspend-param = <0x40000003>;
> > + };
> > +
> > + cpu_mid2_c2: cpu-mid2-c2 {
> > + compatible = "arm,idle-state";
> > +
> > + entry-latency-us = <130>;
> > + exit-latency-us = <274>;
> > + min-residency-us = <2720>;
> > +
> > + idle-state-name = "cpu-mid2-c2";
> > + local-timer-stop;
> > +
> > + arm,psci-suspend-param = <0x40000003>;
> > + };
> > +
> > + cpu_big_c2: cpu-big-c2 {
> > + compatible = "arm,idle-state";
> > +
> > + entry-latency-us = <110>;
> > + exit-latency-us = <413>;
> > + min-residency-us = <3950>;
> > +
> > + idle-state-name = "cpu-big-c2";
> > + local-timer-stop;
> > +
> > + arm,psci-suspend-param = <0x40000003>;
> > + };
> > + };
> > +
> > + domain-idle-states {
> > + cluster_1_c3: cluster-1-c3 {
> > + compatible = "domain-idle-state";
> > +
> > + entry-latency-us = <325>;
> > + exit-latency-us = <553>;
> > + min-residency-us = <10000>;
> > +
> > + idle-state-name = "cluster-1-c3";
> > +
> > + arm,psci-suspend-param = <0x40010033>;
> > + };
> > +
> > + cluster_2_c3: cluster-2-c3 {
> > + compatible = "domain-idle-state";
> > +
> > + entry-latency-us = <345>;
> > + exit-latency-us = <673>;
> > + min-residency-us = <10000>;
> > +
> > + idle-state-name = "cluster-2-c3";
> > +
> > + arm,psci-suspend-param = <0x40010033>;
> > + };
> > +
> > + cluster_c4_deep: cluster-c4-deep {
> > + compatible = "domain-idle-state";
> > +
> > + entry-latency-us = <510>;
> > + exit-latency-us = <1027>;
> > + min-residency-us = <10000>;
> > +
> > + idle-state-name = "cluster-c4-deep";
> > +
> > + arm,psci-suspend-param = <0x40020333>;
> > + };
> > + };
> > + };
> > +
> > + memory: memory at 80000000 {
> > + device_type = "memory";
> > + /* We expect the bootloader to fill in the size */
> > + reg = <0x0 0x80000000 0x0 0x0>;
> > + };
>
> The memory node should go to the DTS (or common DTSI). It's not part of
> SoC usually.
>
> Also, add short comment why do you need label. It will cause
> dt-style-check warning.
>
>
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > +
> > + cpu_pd0: power-domain-cpu0 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_lit_c2>;
> > + power-domains = <&cpu_top_cl>;
> > + };
> > +
> > + cpu_pd1: power-domain-cpu1 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_lit_c2>;
> > + power-domains = <&cpu_top_cl>;
> > + };
> > +
> > + cpu_pd2: power-domain-cpu2 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_mid1_c2>;
> > + power-domains = <&cpucl1>;
> > + };
> > +
> > + cpu_pd3: power-domain-cpu3 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_mid1_c2>;
> > + power-domains = <&cpucl1>;
> > + };
> > +
> > + cpu_pd4: power-domain-cpu4 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_mid1_c2>;
> > + power-domains = <&cpucl1>;
> > + };
> > +
> > + cpu_pd5: power-domain-cpu5 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_mid2_c2>;
> > + power-domains = <&cpucl2>;
> > + };
> > +
> > + cpu_pd6: power-domain-cpu6 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_mid2_c2>;
> > + power-domains = <&cpucl2>;
> > + };
> > +
> > + cpu_pd7: power-domain-cpu7 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cpu_big_c2>;
> > + power-domains = <&cpucl2>;
> > + };
> > +
> > + cpucl1: power-domain-cluster-1 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cluster_1_c3>;
> > + power-domains = <&cpu_top_cl>;
> > + };
> > +
> > + cpucl2: power-domain-cluster-2 {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cluster_2_c3>;
> > + power-domains = <&cpu_top_cl>;
> > + };
> > +
> > + cpu_top_cl: power-domain-top-cluster {
> > + #power-domain-cells = <0>;
> > + domain-idle-states = <&cluster_c4_deep>;
> > + };
> > + };
> > +
> > + reserved_memory: reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + /*
> > + * Store ramoops at a known location in DRAM, for access by the ABL
> > + * following a crash-reset.
> > + */
> > + ramoops at 95200000 {
> > + compatible = "ramoops";
> > + reg = <0x0 0x95200000 0x0 0x400000>;
> > + console-size = <0x200000>;
> > + pmsg-size = <0x200000>;
> > + };
> > +
> > + /* bootloader logs */
> > + bldr_log_reserved: bldr-log-reserved at 95600000 {
> > + reg = <0x0 0x95600000 0x0 0x100000>;
> > + no-map;
> > + };
> > +
> > + /* gsa logs */
> > + gsa_reserved_log: gsa-reserved-log at a61b0000 {
> > + reg = <0x0 0xa61b0000 0x0 0x00004000>;
> > + no-map;
> > + };
> > +
> > + /* Android BootLoader (ABL) for ramdump/coredump processing */
> > + abl at be000000 {
> > + reg = <0x0 0xbe000000 0x0 0x1000000>;
> > + no-map;
> > + };
> > + };
> > +
> > + soc: soc at 0 {
> > + compatible = "simple-bus";
> > + ranges = <0 0 0 0 0x10 0>;
> > +
> > + dma-ranges = <0 0 0 0 0x10 0>;
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + gic: interrupt-controller at 5880000 {
> > + compatible = "arm,gic-v3";
> > + reg = <0 0x05880000 0 0x10000>,
> > + <0 0x05900000 0 0x200000>;
>
> In some other places you use hex everywhere, also for '0' (so '0x0').
> Switch to consistent 0x0 everywhere for new code.
>
> > + ranges;
>
> Why ranges? There is no MSI child node with unit address.
>
> > +
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + #interrupt-cells = <4>;
> > + interrupt-controller;
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> > +
> > + ppi-partitions {
> > + ppi_cluster0: interrupt-partition-0 {
> > + affinity = <&hayes_0 &hayes_1
> > + &hunter_0 &hunter_1 &hunter_2
> > + &hunter_3 &hunter_4>;
> > + };
> > +
> > + ppi_cluster1: interrupt-partition-1 {
> > + affinity = <&hunterelp_0>;
> > + };
> > + };
> > + };
> > +
> > + lsion_cli16_uart: serial at db62000 {
> > + compatible = "google,lga-uart", "snps,dw-apb-uart";
> > + reg = <0 0x0db62000 0 0x100>;
> > +
> > + clock-frequency = <200000000>;
> > + interrupts = <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH 0>;
> > + reg-io-width = <4>;
> > + reg-shift = <2>;
> > +
> > + status = "disabled";
> > + };
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts =
> > + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
>
> Join line:
>
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
>
> even if it goes beyond 80 char limit. That's fine, exceptions are
> allowed and one line makes 'greps' or 'seds' easier.
>
> > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
> > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>,
> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW) 0>;
> > + };
> > +
> > + /*
> > + * The Pixel bootloader considers it a fatal error if it doesn't find
> > + * a `ufs0` alias so it can add calibration data to the node. Until
>
> Fake node is ok, but alias won't fly because aliases are not allowed for
> ufs. Well, would work 10 years ago, but this is a device from ~2025 (so
> SoC maybe a bit earlier), thus Google already knew that they MUST talk
> with upstream open source maintainers before they ship such ABI.
>
> They did not talk, so you reap what you sow.
>
> There is no more excuse for a vendor to ignore open source and push
> whatever-ABI-they-wish into their product, if they ever want to upstream
> that product.
>
> I know it is not your fault, obviously. And I know that not much you can
> do, so that is not rant towards you nor towards Doug.
>
> You will have to keep this part of patch out of tree or fix the Pixel
> bootloader.
I've dropped the ufs0 alias in v3 and added some glue to our build
system so things still boot while we await a new bootloader that
doesn't treat this as a fatal error.
Thanks,
Peter.
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