[PATCH v6 1/9] iommu/arm-smmu-v3: Handle ARM erratum for CONT under invalidation with SVA

[Mark Rutland]

Hi Jason,

Nit on terminology below.

On Wed, Sep 16, 2026 at 09:27:42PM -0300, Jason Gunthorpe wrote:
> The erratum (MMU-700: #3777127, S3: #3673557) deals with under
> invalidation of a CONT PTE grouping in the SMMU. The recommended work
> around is to use a Range Invalidate (RIL) that spans the entire CONT. The
> only user of CONT in the kernel right now is through SVA sharing a CPU
> page table that contains a CONT created by the mm.

As someone familiar with VMSA, I've never seen "RIL" used to describe a
range invalidate and I think using that in the code below is confusing.
I *think* "RIL" has come from "SMMUv3.2-RIL", which is the SMMU feature
for Range Invalidate *and* Level hint, where "RI" is Range Invalidate,
and "L" is Level.

Can we please spell that out as "range invalidate" or "range op"
(matching the arm64 architecture code) rather than "RIL"?

That'll be easier to follow, especially as nothing in the code mentions
what "RIL" means -- that's only mentioned in this commit message.

Mark.