[PATCH v5 03/15] iommu/arm-smmu-v3: Add Q_POS() macro

[Jonathan Cameron]

On Tue, 15 Sep 2026 09:38:15 -0700
Nicolin Chen <nicolinc at nvidia.com> wrote:

> A queue position, the wrap bit combined with the index, is Q_WRP | Q_IDX.
> It is a (max_n_shift + 1)-bit value that wraps at twice the queue capacity.
> queue_inc_cons(), queue_sync_cons_ovf(), and queue_inc_prod_n() currently
> compute such positions by open-coding the two macros at each call site.
> 
> Add a Q_POS() macro and switch the open-coded sites to it.
> 
> A subsequent change will build a Q_DIFF() on it, to count the entries that
> a queue pointer moved past.
> 
> No functional change intended.
> 
> Assisted-by: LLM
> Signed-off-by: Nicolin Chen <nicolinc at nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron at oss.qualcomm.com>