[PATCH] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW1 efuse node for silicon revision

[Judith Mendez]

Hi Udit,

On 9/15/26 11:40 AM, Kumar, Udit wrote:
> 
> Hi Judith,
> 
> On 9/15/2026 5:43 AM, Judith Mendez wrote:
>> Add efuse node for GP_SW1 register at offset 0x230. The GP_SW1
>> efuse register is used to determine AM62Px silicon revision.
>> Reference efuse cell from chipid node via nvmem-cells.
>>
>> Signed-off-by: Judith Mendez <jm at ti.com>
>> ---
>>   .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi  | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
>> index 8612b45e665cf..0f00e9d87f8ba 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
>> @@ -19,9 +19,23 @@ wkup_conf: bus at 43000000 {
>>   		chipid: chipid at 14 {
>>   			compatible = "ti,am654-chipid";
>>   			reg = <0x14 0x4>;
>> +			nvmem-cells = <&gpsw1>;
>> +			nvmem-cell-names = "gpsw1";
>>   			bootph-all;
>>   		};
>>   
>> +		gpsw_efuse: efuse at 230 {
>> +			compatible = "ti,am62p-efuse", "socionext,uniphier-efuse";
>> +			reg = <0x230 0x10>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			bootph-all;
>> +
>> +			gpsw1: gpsw1 at 4 {
>> +				reg = <0x4 0x4>;
>> +			};
> 
> For J722S, this register this marked as reserved,
> Could you update in am62-p specific dt.

Right, let me see what I can do.

Thanks for reviewing.

~ Judith

> 
> Thanks
> 
>> +		};
>> +
>>   		opp_efuse_table: syscon at 18 {
>>   			compatible = "ti,am62-opp-efuse-table", "syscon";
>>   			reg = <0x18 0x4>;
>