[PATCH v4 06/20] dt-bindings: soc: starfive: Add starfive,jh7110-vout-subsystem
Michal Wilczynski
m.wilczynski at samsung.com
Tue Sep 15 08:32:14 PDT 2026
The JH7110 groups its display hardware into a video output subsystem,
dom_vout_top, covering the DC8200, the HDMI transmitter, the video
output clock generator and the video output system controller.
They share one NoC port whose clock and reset gate access to every
register in the region, and the region sits in the PD_VOUT power
domain. Describe the subsystem as a bus node so those resources are
owned by the block that shares them, rather than by whichever consumer
happens to probe first.
Signed-off-by: Michal Wilczynski <m.wilczynski at samsung.com>
---
.../starfive/starfive,jh7110-vout-subsystem.yaml | 218 +++++++++++++++++++++
1 file changed, 218 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..3306c4068493ec30b3863db6ff7eb47b13d55240
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
@@ -0,0 +1,218 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsystem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 video output subsystem
+
+maintainers:
+ - Michal Wilczynski <m.wilczynski at samsung.com>
+
+description:
+ The JH7110 groups its display hardware into a video output subsystem, named
+ dom_vout_top in the documentation. It covers the DC8200 display controller,
+ the HDMI transmitter, the video output clock generator and the video output
+ system controller, all behind one NoC port. That port's clock and reset gate
+ access to every register in the region, and the region sits in the PD_VOUT
+ power domain, so this node owns those resources on behalf of its children.
+
+properties:
+ compatible:
+ const: starfive,jh7110-vout-subsystem
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: NoC display bus clock.
+
+ resets:
+ maxItems: 1
+ description: NoC display bus reset.
+
+ power-domains:
+ maxItems: 1
+
+ dma-noncoherent: true
+
+ ranges: true
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+patternProperties:
+ "^display@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-dc8200
+
+ "^hdmi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: starfive,jh7110-hdmi-subsystem
+
+ "^syscon@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-vout-syscon
+
+ "^clock-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: starfive,jh7110-voutcrg
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - power-domains
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+ #include <dt-bindings/power/starfive,jh7110-pmu.h>
+ #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ display-subsystem at 29400000 {
+ compatible = "starfive,jh7110-vout-subsystem";
+ reg = <0x0 0x29400000 0x0 0x200000>;
+ ranges;
+ #address-cells = <2>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
+ dma-noncoherent;
+ power-domains = <&pwrc JH7110_PD_VOUT>;
+ resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
+ #size-cells = <2>;
+
+ display at 29400000 {
+ compatible = "starfive,jh7110-dc8200", "verisilicon,dc";
+ reg = <0x0 0x29400000 0x0 0x2800>;
+ clocks = <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
+ <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>;
+ clock-names = "core", "axi", "ahb", "pix0", "pix1";
+ interrupts = <95>;
+ resets = <&voutcrg JH7110_VOUTRST_DC8200_CORE>,
+ <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
+ <&voutcrg JH7110_VOUTRST_DC8200_AHB>;
+ reset-names = "core", "axi", "ahb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpu_out_dpi0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi at 29590000 {
+ compatible = "starfive,jh7110-hdmi-subsystem";
+ reg = <0x0 0x29590000 0x0 0x4000>;
+
+ controller {
+ compatible = "starfive,jh7110-inno-hdmi-controller";
+ clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+ <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+ <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
+ <&hdmi_phy>;
+ clock-names = "pclk", "mclk", "bclk", "pixel";
+ interrupts = <99>;
+ phys = <&hdmi_phy>;
+ resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+ starfive,vout-syscon = <&vout_syscon>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ hdmi_in: endpoint {
+ remote-endpoint = <&dpu_out_dpi0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+ };
+
+ hdmi_phy: phy {
+ compatible = "starfive,jh7110-inno-hdmi-phy";
+ #clock-cells = <0>;
+ clocks = <&xin24m>;
+ #phy-cells = <0>;
+ };
+ };
+
+ vout_syscon: syscon at 295b0000 {
+ compatible = "starfive,jh7110-vout-syscon", "syscon";
+ reg = <0x0 0x295b0000 0x0 0x10000>;
+ };
+
+ voutcrg: clock-controller at 295c0000 {
+ compatible = "starfive,jh7110-voutcrg";
+ reg = <0x0 0x295c0000 0x0 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
+ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
+ <&hdmi_phy>;
+ clock-names = "vout_src", "vout_top_ahb",
+ "vout_top_axi", "vout_top_hdmitx0_mclk",
+ "i2stx0_bclk", "hdmitx0_pixelclk";
+ power-domains = <&pwrc JH7110_PD_VOUT>;
+ #reset-cells = <1>;
+ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
+ };
+ };
+ };
+...
--
2.34.1
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