[PATCH net-next v3 2/6] dt-bindings: net: xlnx,xxv-ethernet: Add Xilinx XXV 10G/25G Ethernet

[Gupta, Suraj]

Hi Andrew,

On 9/1/2026 10:31 PM, Gupta, Suraj wrote:
> 
> 
> On 9/1/2026 8:01 PM, Andrew Lunn wrote:
>> On Tue, Sep 01, 2026 at 08:48:18AM +0530, Gupta, Suraj wrote:
>>>
>>>
>>> On 9/1/2026 7:57 AM, Andrew Lunn wrote:
>>>>> +  The Xilinx XXV Ethernet Subsystem implements a 10G/25G Ethernet 
>>>>> MAC with an
>>>>> +  in-core PCS/PMA driving a high-speed serial transceiver. It 
>>>>> supports the
>>>>> +  10GBASE-R and 25GBASE-R line rates, with 25G operation following 
>>>>> the 25G
>>>>> +  Ethernet Consortium specification. It has no external MDIO PHY
>>>>
>>>> What about MDIO bus?
>>>>
>>>>     Andrew
>>>
>>> The 10G/25G (XXV) Ethernet Subsystem IP does not provide an MDIO master.
>>
> 
> 
> I'll try to make the overall architecture clear, please let me know if I 
> miss something and additional details needed. The datapath is:
> 
> DMA (AXIDMA/ MCDMA) <-> (XXV MAC + PCS/PMA) <-> GT serial transceiver <- 
>  > optical module / backplane.
> MAC's in-core PCS/PMA drives a hardened GT (SerDes) transceiver directly 
> at 10GBASE-R / 25GBASE-R, and the GT is configured over its DRP 
> interface (the "drp" clock in this binding). There is no discrete PHY 
> chip and no MDIO or I2C master inside the IP.
> 
> XXV ethernet PG: https://docs.amd.com/r/en-US/pg210-25g-ethernet
> 
>> O.K. Please change the wording to make that clear. There are plenty to
>> 10G PHYs available, but it seems like you do not consider that a use
>> case.
>>
> 
> Correct, the IP has no MDIO bus master, so an externally MDIO-managed 
> PHY is not a supported use case. I will reword the description in v4 to 
> state that explicitly, e.g.:
> "The subsystem has an in-core PCS/PMA that drives a GT serial 
> transceiver; it has no MDIO bus master and is therefore not managed 
> through an external MDIO PHY. Link state is taken from the MAC's own 
> status registers."
> 
>> Has the MDIO bus master been replaced with I2C? I assume you intend
>> this device to be paired by an SFP cage, so an I2C bus will be
>> required. Is that a different IP which needs to be licensed?
>>
> 
> The XXV Ethernet core contains neither an MDIO nor an I2C master. When a 
> hardware design pairs it with an SFP/SFP+ cage, only the high-speed data 
> path runs through this IP: the in-core PCS/PMA drives the GT 
> transceiver, whose serial TX/RX lanes connect to the module. The module 
> management side-band -- I2C for the module EEPROM/diagnostics is not 
> part of this IP. It is provided by separate board logic, i.e. a 
> different IP: a standard AXI IIC controller. Those are general-purpose 
> soft cores from the standard Vivado IP catalog; each has its own 
> devicetree node and binding, so the SFP management path looks outside 
> the scope of this Ethernet binding.
> Please let me know if I should describe sfp in this binding.
> 
> 
>>> The contents of the appropriate MDIO registers are available in the 
>>> IP control &
>>> status registers.
>>
>> What does that mean?
>>
>>       Andrew
> 
> I meant that the PCS/link state a driver would normally read from a PHY 
> over MDIO (link up, resolved speed, block-lock/RX status) is exposed 
> directly in the XXV IP's control & status registers, because the PCS/PMA 
> is in-core.
> 
> 
> Thanks,
> Suraj

Please let me know if I should provide any additional details.

Also, would you recommend that I send a v4 addressing the commit message 
and comment updates we discussed, or should I wait for further review 
feedback on the series?

Thanks,
Suraj