[PATCH 10/13] arm64: dts: apple: t8122: Fix most property-order dt-style-check issues

[Sven Peter]

Hi,

On 9/9/26 12:27, Janne Grunau wrote:
> t8122-pmgr.dtsi is left unchanged because future additions or
> modifications will be sparse.
>
> Not fixed are
>
> | [property-order] property 'd-cache-size' out of canonical order (should sort before 'enable-method')
>
> for all CPU nodes to keep cache related properties together. A blank
> line is added before 'd-cache-size' to attenuate this grouping for human
> consumption.
>
> Signed-off-by: Janne Grunau <j at jannau.net>
> ---
[...]
>   
>   			status = "disabled";
> @@ -270,16 +278,16 @@ fpwm1: pwm at 2a1044000 {
>   		serial0: serial at 2a1200000 {
>   			compatible = "apple,s5l-uart";
>   			reg = <0x2 0xa1200000 0x0 0x1000>;
> -			reg-io-width = <4>;
> +			clocks = <&clkref>, <&clkref>;
> +			clock-names = "uart", "clk_uart_baud0";
>   			interrupt-parent = <&aic>;
>   			interrupts = <AIC_IRQ 757 IRQ_TYPE_LEVEL_HIGH>;
>   			/*
>   			 * TODO: figure out the clocking properly, there may
>   			 * be a third selectable clock.
>   			 */
> -			clocks = <&clkref>, <&clkref>;
> -			clock-names = "uart", "clk_uart_baud0";

Please also move the comment so that it stays together with clocks = ...;



Sven