[PATCH] drivers/perf: apple_m1: Add macOS 27 M2 Event

[Myria Sarvay via B4 Relay]

From: Myria Sarvay <myrialsarvay at gmail.com>

This patch adds another known PMU event that can be found under
/usr/share/kpep on macOS 27 for M2 macs. INST_SIMD_ALU_VEC purports to
count "Retired non-load/store vector Advanced SIMD instructions", and as
we already noted, can only be registered on counter 7. Though this event
only shows up on the M2 kpep records, it can be set on M1 CPUs, and
records something.

Link: https://github.com/0ax1/apmc/blob/9cff99a9df2ae055f1e3065c64f633e38bb6beec/counters/m2.md
Signed-off-by: Myria Sarvay <myrialsarvay at gmail.com>
---
 drivers/perf/apple_m1_cpu_pmu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 81b6f1a62349..1f73c8a77462 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -81,7 +81,7 @@ enum m1_pmu_events {
 	M1_PMU_PERFCTR_INST_SIMD_ALU				= 0x9a,
 	M1_PMU_PERFCTR_INST_LDST				= 0x9b,
 	M1_PMU_PERFCTR_INST_BARRIER				= 0x9c,
-	M1_PMU_PERFCTR_UNKNOWN_9f				= 0x9f,
+	M1_PMU_PERFCTR_INST_SIMD_ALU_VEC			= 0x9f,
 	M1_PMU_PERFCTR_L1D_TLB_ACCESS				= 0xa0,
 	M1_PMU_PERFCTR_L1D_TLB_MISS				= 0xa1,
 	M1_PMU_PERFCTR_L1D_CACHE_MISS_ST			= 0xa2,
@@ -150,7 +150,7 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] = {
 	[M1_PMU_PERFCTR_INST_SIMD_ALU]				= BIT(7),
 	[M1_PMU_PERFCTR_INST_LDST]				= BIT(7),
 	[M1_PMU_PERFCTR_INST_BARRIER]				= ONLY_5_6_7,
-	[M1_PMU_PERFCTR_UNKNOWN_9f]				= BIT(7),
+	[M1_PMU_PERFCTR_INST_SIMD_ALU_VEC]			= BIT(7),
 	[M1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC]		= ONLY_5_6_7,
 	[M1_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC]		= ONLY_5_6_7,
 	[M1_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC]			= ONLY_5_6_7,

---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260912-m2-9f-pmu-name-789cf6239f79

Best regards,
--  
Myria Sarvay <myrialsarvay at gmail.com>