[PATCH 08/10] arm64: dts: exynos5433: Re-order nodes to match coding style
Krzysztof Kozlowski
krzysztof.kozlowski at oss.qualcomm.com
Fri Sep 11 03:19:16 PDT 2026
Re-order a few nodes to match coding style - ordering by the name, as
pointed out by dt-check-style, e.g.:
gs101.dtsi:476: [child-name-order] child node 'ect' out of name order
gs101.dtsi:479: [child-name-order] child node 'clock-1' out of name order
While moving the lines, move also linux,code to the end to follow convention.
This is not complete re-ordering of all nodes and children of "soc" node
are left as is.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at oss.qualcomm.com>
---
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 28 ++---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 132 ++++++++++-----------
2 files changed, 80 insertions(+), 80 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 0ad02a098765..a85afdde9c41 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -56,6 +56,13 @@ memory at 20000000 {
gpio-keys {
compatible = "gpio-keys";
+ homepage-key {
+ gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+ label = "homepage key";
+ debounce-interval = <10>;
+ linux,code = <KEY_MENU>;
+ };
+
power-key {
gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
@@ -76,13 +83,6 @@ volume-down-key {
label = "volume-down key";
debounce-interval = <10>;
};
-
- homepage-key {
- gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_MENU>;
- label = "homepage key";
- debounce-interval = <10>;
- };
};
i2c_max98504: i2c-13 {
@@ -103,13 +103,6 @@ max98504: amplifier at 31 {
};
};
- vph_pwr_regulator: regulator-vph-pwr {
- compatible = "regulator-fixed";
- regulator-name = "VPH_PWR";
- regulator-min-microvolt = <4200000>;
- regulator-max-microvolt = <4200000>;
- };
-
irda_regulator: regulator-irda {
compatible = "regulator-fixed";
enable-active-high;
@@ -117,6 +110,13 @@ irda_regulator: regulator-irda {
regulator-name = "irda_regulator";
};
+ vph_pwr_regulator: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "VPH_PWR";
+ regulator-min-microvolt = <4200000>;
+ regulator-max-microvolt = <4200000>;
+ };
+
sound {
compatible = "samsung,tm2-audio";
audio-codec = <&wm5110>, <&hdmi>;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index d318c87effaa..3e67d9091a19 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -90,72 +90,6 @@ core3 {
};
};
- cpu0: cpu at 100 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x100>;
- clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
- clock-names = "apolloclk";
- operating-points-v2 = <&cluster_a53_opp_table>;
- #cooling-cells = <2>;
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&cluster_a53_l2>;
- };
-
- cpu1: cpu at 101 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x101>;
- operating-points-v2 = <&cluster_a53_opp_table>;
- #cooling-cells = <2>;
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&cluster_a53_l2>;
- };
-
- cpu2: cpu at 102 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x102>;
- operating-points-v2 = <&cluster_a53_opp_table>;
- #cooling-cells = <2>;
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&cluster_a53_l2>;
- };
-
- cpu3: cpu at 103 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x103>;
- operating-points-v2 = <&cluster_a53_opp_table>;
- #cooling-cells = <2>;
- i-cache-size = <0x8000>;
- i-cache-line-size = <64>;
- i-cache-sets = <256>;
- d-cache-size = <0x8000>;
- d-cache-line-size = <64>;
- d-cache-sets = <128>;
- next-level-cache = <&cluster_a53_l2>;
- };
-
cpu4: cpu at 0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
@@ -222,6 +156,72 @@ cpu7: cpu at 3 {
next-level-cache = <&cluster_a57_l2>;
};
+ cpu0: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
+ clock-names = "apolloclk";
+ operating-points-v2 = <&cluster_a53_opp_table>;
+ #cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
+ };
+
+ cpu1: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster_a53_opp_table>;
+ #cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
+ };
+
+ cpu2: cpu at 102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster_a53_opp_table>;
+ #cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
+ };
+
+ cpu3: cpu at 103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ operating-points-v2 = <&cluster_a53_opp_table>;
+ #cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&cluster_a53_l2>;
+ };
+
cluster_a57_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
--
2.53.0
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