[PATCH v5 2/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6

[Diederik de Haas]

On Thu Sep 10, 2026 at 10:07 PM CEST, Ricardo Pardini via B4 Relay wrote:
> From: Ricardo Pardini <ricardo at pardini.net>
>
> The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs
> behind pcie2x1l0 and pcie2x1l2.
>
> Describe the fixed function nodes and attach ethernet0/ethernet1
> aliases, so that U-Boot's fdt_fixup_ethernet() can fill in the MAC
> from its ethaddr/eth1addr env. The on-NIC EEPROMs on this board are
> not pre-programmed with a unique MAC, so this gives a stable MAC
> across boots that both U-Boot and the kernel agree on.
>
> Signed-off-by: Ricardo Pardini <ricardo at pardini.net>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
> index cfdb5c13f8606..550358a756618 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
> @@ -20,6 +20,8 @@ / {
>  	compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
>  
>  	aliases {
> +		ethernet0 = &rtl_eth0;
> +		ethernet1 = &rtl_eth1;
>  		mmc0 = &sdhci;
>  		mmc1 = &sdmmc;
>  	};
> @@ -644,6 +646,20 @@ &pcie2x1l0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie2_0_rst>;

The new pinctrl reference is ``pcie_25glan_perstb_b_pin``, so this patch needs
to be rebased.

>  	status = "okay";
> +
> +	pcie at 0,0 {
> +		reg = <0x200000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x21 0x2f>;
> +
> +		rtl_eth0: ethernet at 0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x210000 0 0 0 0>;
> +		};

Described on page 23 of the schematic titled '2.5G Ethernet B' and ``U12``
(ie RTL8125BG) is connected to LAN2 which has ``ETH2`` as label on the case.

> +	};
>  };
>  
>  &pcie2x1l1 {
> @@ -660,6 +676,20 @@ &pcie2x1l2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie2_2_rst>;

The new pinctrl reference is ``pcie_25glan_perstb_pin``.

>  	status = "okay";
> +
> +	pcie at 0,0 {
> +		reg = <0x400000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x41 0x4f>;
> +
> +		rtl_eth1: ethernet at 0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x410000 0 0 0 0>;
> +		};

Described on page 22 of the schematic titled '2.5G Ethernet A' and ``U10``
(ie RTL8125BG) is connected to LAN1 which has ``ETH1`` as label on the case.

So this results in:
ETH1 -> rtl_eth1
ETH2 -> rtl_eth0

This sounds like a recipe for confusion and/or potential future mistakes.
I think using ``rtl_eth1`` and ``rtl_eth2`` would be less confusing, but
I'm fine with another construct which achieves a similar thing.

Cheers,
  Diederik

> +	};
>  };
>  
>  &pcie30phy {