[PATCH v4] driver: fpga: xilinx-selectmap: add csi and rdwr support

[Xu Yilun]

> I would change v5 commit message to:
> """
>     The driver requests the optional CSI_B and RDWR_B GPIOs with
>     GPIOD_OUT_HIGH and never touches them again. That flag carries a
>     logical value, so both signals end up asserted on every board,
>     whatever polarity the device tree states.

Yeah, that's clear now.

> 
>     Keeping them asserted works as long as a single FPGA owns the
>     SelectMAP port. That FPGA is the only device on the bus, so it may
>     stay selected, and the driver never reads from it, so the port may
>     stay in write mode.

I think keeping them asserted is a bad idea even for single FPGA, isn't
it?

> 
>     It stops working as soon as two FPGAs share one SelectMAP data bus,
>     which is the case CSI_B exists for. Both devices are selected all
>     the time, so every byte written for one of them is clocked into the
>     other as well, and neither can be configured on its own.
> 
>     CSI_B (Chip Select) selects the target FPGA. Assert it before the
>     configuration data is transferred and deassert it afterwards, so that
>     only the intended device sees the bus cycles.

What if we re-program the 2 FPGAs at the same time? Is there still
chance the 2 CS lines are all asserted? Can they be correctly
re-programmed in this case?

I mean I think this patch does fix the problem of "always assertion",
which is good to me. But the changelog seems stop me, it talks all about
2 FPGAs sharing the same bus, which seems more complex than just
manipulating the CS.

Thanks,
Yilun

> 
>     RDWR_B (Read/Write) selects the transfer direction on the SelectMAP
>     interface. Assert it for the write cycles that carry the bitstream and
>     deassert it afterwards. UG570 wants RDWR_B settled before CSI_B is
>     asserted, a change while the device is selected aborts the
>     configuration on the next CCLK.
> 
>     Both are requested with GPIOD_OUT_LOW now, the logical 0 that leaves
>     them deasserted, and their descriptors are kept in the driver private
>     data.
> 
>     A board with one FPGA keeps working. SelectMAP allows the bitstream to
>     be loaded non-continuously, with CSI_B deasserted between the data
>     transfers, and a deselected device ignores the bus.
> """