[PATCH v5 9/9] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE

Jason Gunthorpe jgg at nvidia.com
Mon Sep 7 12:39:24 PDT 2026


On Mon, Sep 07, 2026 at 02:44:22PM +0000, Mostafa Saleh wrote:
> On Tue, Sep 01, 2026 at 02:49:58PM -0300, Jason Gunthorpe wrote:
> > If DS is supported then SCALE can go up to 39. Compute a scale max that is
> > compatible for the entire invs list.
> 
> I see in some places scale is still assumed to 32 as in:
> - arm_smmu_ril_init_end
> - arm_smmu_tlbi_calc_range

Neither of those are scale, they are the range of NUM:

	first.scale = fls64((num_tg - 1) / 32);

ie what scale do you need to fit in at most 32 NUM.

I will add a constant "MAX_RIL_NUM", it will be clearer.

Jason



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