[PATCH v5 3/3] arm64: dts: cix: add support for cix sky1 resets

[Gary Yang]

There are two reset conctrollers on Cix Sky1 Soc. One is located in S0
domain, and the other is located in S0 and S5 domain.

Signed-off-by: Gary Yang <gary.yang at cixtech.com>
Signed-off-by: Peter Chen <peter.chen at cixtech.com>
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 64b76905cbff..a72448cc97e3 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -348,6 +348,17 @@ i3c1: i3c at 4100000 {
 			status = "disabled";
 		};
 
+		syscon: syscon at 4160000 {
+			compatible = "cix,sky1-system-controller", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0x4160000 0x0 0x100>;
+
+			src_fch: reset-controller {
+				compatible = "cix,sky1-rst-fch";
+				#reset-cells = <1>;
+			};
+		};
+
 		iomuxc: pinctrl at 4170000 {
 			compatible = "cix,sky1-pinctrl";
 			reg = <0x0 0x04170000 0x0 0x1000>;
@@ -568,6 +579,17 @@ ppi_partition1: interrupt-partition-1 {
 			};
 		};
 
+		s5_syscon: s5-syscon at 16000000 {
+			compatible = "cix,sky1-s5-system-controller", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0x16000000 0x0 0x1000>;
+
+			src: reset-controller {
+				compatible = "cix,sky1-rst";
+				#reset-cells = <1>;
+			};
+		};
+
 		iomuxc_s5: pinctrl at 16007000 {
 			compatible = "cix,sky1-pinctrl-s5";
 			reg = <0x0 0x16007000 0x0 0x1000>;
-- 
2.49.0