[PATCH v10 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU
Suzuki K Poulose
suzuki.poulose at arm.com
Mon Jan 26 09:22:29 PST 2026
On 22/01/2026 02:08, Jie Gan wrote:
> Add an interrupt property to CTCU device. The interrupt will be triggered
> when the data size in the ETR buffer exceeds the threshold of the
> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
> of CTCU device will enable the interrupt.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Reviewed-by: Mike Leach <mike.leach at linaro.org>
> Signed-off-by: Jie Gan <jie.gan at oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index c969c16c21ef..ac27a8b89085 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -39,6 +39,11 @@ properties:
> items:
> - const: apb
>
> + interrupts:
> + items:
> + - description: Interrupt for the ETR device connected to in-port0.
> + - description: Interrupt for the ETR device connected to in-port1.
Is this all the hardware supports ? i.e., can it only have two ports
ever ? If not, why restrict it to two ?
Suzuki
> +
> label:
> description:
> Description of a coresight device.
> @@ -60,6 +65,8 @@ additionalProperties: false
>
> examples:
> - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> ctcu at 1001000 {
> compatible = "qcom,sa8775p-ctcu";
> reg = <0x1001000 0x1000>;
> @@ -67,6 +74,9 @@ examples:
> clocks = <&aoss_qmp>;
> clock-names = "apb";
>
> + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
> +
> in-ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
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