[PATCH v3] arm64: errata: Workaround for SI L1 downstream coherency issue

[Will Deacon]

On Wed, 14 Jan 2026 14:52:41 +0000, Lucas Wei wrote:
> When software issues a Cache Maintenance Operation (CMO) targeting a
> dirty cache line, the CPU and DSU cluster may optimize the operation by
> combining the CopyBack Write and CMO into a single combined CopyBack
> Write plus CMO transaction presented to the interconnect (MCN).
> For these combined transactions, the MCN splits the operation into two
> separate transactions, one Write and one CMO, and then propagates the
> write and optionally the CMO to the downstream memory system or external
> Point of Serialization (PoS).
> However, the MCN may return an early CompCMO response to the DSU cluster
> before the corresponding Write and CMO transactions have completed at
> the external PoS or downstream memory. As a result, stale data may be
> observed by external observers that are directly connected to the
> external PoS or downstream memory.
> 
> [...]

Applied to arm64 (for-next/errata), thanks!

[1/1] arm64: errata: Workaround for SI L1 downstream coherency issue
      https://git.kernel.org/arm64/c/3fed7e0059f0

Cheers,
-- 
Will

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