[PATCH v2 8/9] arm64: dts: renesas: ulcb: ulcb-kf: Describe PCIe/USB3.0 clock generator
Geert Uytterhoeven
geert at linux-m68k.org
Fri Jan 23 05:37:21 PST 2026
Hi Marek,
Thanks for your patch!
On Sun, 18 Jan 2026 at 14:51, Marek Vasut
<marek.vasut+renesas at mailbox.org> wrote:
> Describe the 9FGV0841 PCIe and USB3.0 clock generator present on ULCB
> board. The clock generator supplies 100 MHz differential clock for both
> PCIe ports, the USB 3.0 PHY and SATA.
>
> SATA is not yet described in the ULCB DT, therefore the connection to
> this clock generator is not described here either.
>
> The H3 ULCB schematic does describe connection from output DIF7 to
> USB3S1_CLK_*, but these signals do not exist on the SoC, therefore
> this connection is also not described.
That is the case because the first ULCB came with R-Car H3 ES1.0,
which did have two USB3 channels. R-Car H3 ES2.0, M3-W, M3-W+,
and M3-N have only a single USB3 channel.
> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
i.e. will queue in renesas-devel for v6.21.
> --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
> +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
> @@ -352,19 +352,30 @@ &ohci0 {
>
> &pcie_bus_clk {
> clock-frequency = <100000000>;
I will drop the clock-frequency while applying, as there is no point
in changing it in a disabled node.
> + status = "disabled";
> };
>
> @@ -475,6 +486,16 @@ &usb2_phy0 {
> status = "okay";
> };
>
> +&usb3_phy0 {
> + clocks = <&cpg CPG_MOD 328>, <&pcie_usb_clk 6>, <&usb_extal_clk>;
> + status = "okay";
> +};
> +
> +&usb3s0_clk {
> + clock-frequency = <100000000>;
Likewise.
> + status = "disabled";
> +};
> +
> &xhci0 {
> status = "okay";
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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