[PATCH 5/7] clk: sunxi-ng: mux: Add mux read-only clock operations

[Junhui Liu]

The Allwinner A733 SoC introduces some mux clocks (such as the one
indicating the DCXO frequency) that use read-only registers to report
their current hardware configuration. Writing to these registers is not
supported by hardware and should be avoided.

Add ccu_mux_ro_ops to support these clocks, which omit .set_parent()
and .determine_rate() to prevent changing the mux state.

Signed-off-by: Junhui Liu <junhui.liu at pigmoral.tech>
---
 drivers/clk/sunxi-ng/ccu_mux.c | 11 +++++++++++
 drivers/clk/sunxi-ng/ccu_mux.h |  1 +
 2 files changed, 12 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 74f9e98a5d35..d48e7c3e065d 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -277,6 +277,17 @@ const struct clk_ops ccu_mux_ops = {
 };
 EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, "SUNXI_CCU");
 
+const struct clk_ops ccu_mux_ro_ops = {
+	.disable	= ccu_mux_disable,
+	.enable		= ccu_mux_enable,
+	.is_enabled	= ccu_mux_is_enabled,
+
+	.get_parent	= ccu_mux_get_parent,
+
+	.recalc_rate	= ccu_mux_recalc_rate,
+};
+EXPORT_SYMBOL_NS_GPL(ccu_mux_ro_ops, "SUNXI_CCU");
+
 /*
  * This clock notifier is called when the frequency of the of the parent
  * PLL clock is to be changed. The idea is to switch the parent to a
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index eb1172ebbd94..887c164d00f4 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -129,6 +129,7 @@ static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw)
 }
 
 extern const struct clk_ops ccu_mux_ops;
+extern const struct clk_ops ccu_mux_ro_ops;
 
 unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common,
 					  struct ccu_mux_internal *cm,

-- 
2.52.0