[PATCH v2 1/8] arm64: Provide dcache_by_myline_op_nosync helper

[Will Deacon]

On Sat, Dec 27, 2025 at 11:52:41AM +1300, Barry Song wrote:
> From: Barry Song <baohua at kernel.org>
> 
> dcache_by_myline_op ensures completion of the data cache operations for a
> region, while dcache_by_myline_op_nosync only issues them without waiting.
> This enables deferred synchronization so completion for multiple regions
> can be handled together later.
> 
> Cc: Leon Romanovsky <leon at kernel.org>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Will Deacon <will at kernel.org>
> Cc: Marek Szyprowski <m.szyprowski at samsung.com>
> Cc: Robin Murphy <robin.murphy at arm.com>
> Cc: Ada Couprie Diaz <ada.coupriediaz at arm.com>
> Cc: Ard Biesheuvel <ardb at kernel.org>
> Cc: Marc Zyngier <maz at kernel.org>
> Cc: Anshuman Khandual <anshuman.khandual at arm.com>
> Cc: Ryan Roberts <ryan.roberts at arm.com>
> Cc: Suren Baghdasaryan <surenb at google.com>
> Cc: Tangquan Zheng <zhengtangquan at oppo.com>
> Signed-off-by: Barry Song <baohua at kernel.org>
> ---
>  arch/arm64/include/asm/assembler.h  | 24 +++++++++++++++++++-----
>  arch/arm64/kernel/relocate_kernel.S |  3 ++-
>  2 files changed, 21 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index f0ca7196f6fa..b408ed61866f 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -371,14 +371,13 @@ alternative_endif
>   * [start, end) with dcache line size explicitly provided.
>   *
>   * 	op:		operation passed to dc instruction
> - * 	domain:		domain used in dsb instruction
>   * 	start:          starting virtual address of the region
>   * 	end:            end virtual address of the region
>   *	linesz:		dcache line size
>   * 	fixup:		optional label to branch to on user fault
>   * 	Corrupts:       start, end, tmp
>   */
> -	.macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
> +	.macro raw_dcache_by_myline_op op, start, end, linesz, tmp, fixup
>  	sub	\tmp, \linesz, #1
>  	bic	\start, \start, \tmp
>  .Ldcache_op\@:
> @@ -402,14 +401,13 @@ alternative_endif
>  	add	\start, \start, \linesz
>  	cmp	\start, \end
>  	b.lo	.Ldcache_op\@
> -	dsb	\domain

Naming nit, but I'd prefer this to be dcache_by_myline_op_nosync() for
consistency with the other macros that you're adding. The 'raw' prefix
is used by raw_dcache_line_size() to indicate that we're getting the
value from the underlying hardware register.

>  
>  	_cond_uaccess_extable .Ldcache_op\@, \fixup
>  	.endm
>  
>  /*
>   * Macro to perform a data cache maintenance for the interval
> - * [start, end)
> + * [start, end) and wait for completion
>   *
>   * 	op:		operation passed to dc instruction
>   * 	domain:		domain used in dsb instruction
> @@ -420,7 +418,23 @@ alternative_endif
>   */
>  	.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
>  	dcache_line_size \tmp1, \tmp2
> -	dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
> +	raw_dcache_by_myline_op \op, \start, \end, \tmp1, \tmp2, \fixup
> +	dsb \domain
> +	.endm

This could just be dcache_by_line_op_nosync() + dsb.

Will